Optical clock recovery using feedback phase rotator with non-linear compensation

• US 10,187,197 B2
• Filed: 07/23/2018
• Issued: 01/22/2019
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: Ciena Corporation
• Original Assignee: Ciena Corporation
• Inventors: Aouini, Sadok, Ben-Hamida, Naim, Kurowski, Christopher, Jakober, Lukas
• Primary Examiner(s): Wong, Linda
• Application Number:
  US16/042,425
• Publication Number:
  US 20180331818A1
• Time in Patent Office: 183 Days
• Field of Search: 375219, 375220, 375222, 375221, 375229-236, 375226, 375240, 37524026, 37524027, 37524028, 37524029, 375254, 375259, 375285, 375284, 375278, 375294, 375293, 375295, 375296, 375306, 375307, 375308, 375312, 375354, 375356, 375 35, 375 5, 375362, 375359, 375371, 375373, 375374, 375375, 375376
• CPC Class Codes: H03L 2207/00 Indexing scheme relating to automatic control of frequency or phase and to synchronisation
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 2207/18 Temporarily disabling, deactivating or stopping the frequency counter or divider
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04B 10/40 Transceivers

Abstract

A method for clock recovery that may include obtaining an output signal from a phase locked loop (PLL) device. The method may further include determining, using a digital phase detector, the output signal, and a transmitter clock signal, an amount of phase difference between the output signal and the transmitter clock signal. The method may further include filtering, using a phase rotator and a digital accumulator, a portion of the amount of phase difference from the output signal to generate a filtered signal.

Claims

1. A receiver apparatus, comprising:

a phase locked loop (PLL) device that includes

an analog phase detector configured to receive a reference signal, and

a voltage-controlled oscillator (VCO) device, wherein the VCO device is configured to generate, based on the reference signal, an output signal;

a phase rotator coupled to the VCO device and the analog phase detector;

a digital phase detector coupled to the VCO device, the digital phase detector configured to determine an amount of phase difference between a transmitter clock signal and the output signal;

a digital accumulator coupled to the digital phase detector, wherein the phase rotator and the digital accumulator are configured, using the amount of phase difference between the transmitter clock signal and the output signal, to filter a portion of the amount of phase difference from the output signal to generate a filtered signal for transmission to the analog phase detector; and

a lookup table circuit coupled to the digital accumulator,

wherein the lookup table circuit is configured to generate a control signal based on a value of the amount of phase difference between the transmitter clock signal and the output signal, and

wherein the control signal is configured to produce, using the phase rotator, a predetermined phase shift in the filtered signal provided as a feedback signal within the PLL device.

2. The apparatus of claim 1,

wherein the lookup table circuit is further configured to provide a plurality of values of the control signal that reduce PLL noise within the feedback loop of the PLL device, and

wherein the plurality of values are based on measurements of corresponding phase adjustment steps within the feedback loop.

3. The apparatus of claim 1,

wherein the digital phase detector is a Godard digital phase detector, and

wherein the transmitter clock signal is extracted from a received signal using Godard binning.

4. The apparatus of claim 1,

wherein the transmitter clock signal is extracted from a serializer-deserializer (SerDes) input signal.

5. The apparatus of claim 1,

wherein the phase rotator decouples a clock recovery bandwidth from a bandwidth of the PLL device.

6. The apparatus of claim 1,

wherein the output signal is a receiver clock signal within a transceiver.

7. A receiver apparatus, comprising:

a phase locked loop (PLL) device that includes

an analog phase detector configured to obtain a reference signal, and

a voltage-controlled oscillator (VCO) device, wherein the VCO device is configured to generate, based on the reference signal, an output signal;

a phase rotator coupled to the VCO device and the analog phase detector;

a first digital phase detector coupled to the VCO device, the first digital phase detector being configured to determine an amount of phase difference between a transmitter clock signal and the output signal;

a digital accumulator coupled to the first digital phase detector, wherein the phase rotator and the digital accumulator are configured, using the amount of phase difference between the transmitter clock signal and the output signal, to filter a portion of the amount of phase difference from the output signal to generate a filtered signal for transmission to the analog phase detector;

a delay element coupled to the phase rotator and the analog phase detector;

a second digital phase detector coupled to the delay element and the phase rotator, the second digital phase detector being configured to determine an amount of PLL noise based on the reference signal and the filtered signal; and

a digital filter coupled to the second digital phase detector,

wherein the delay element and the digital filter are configured, using the amount of PLL noise, to reduce a portion of the amount of PLL noise from the filtered signal.

8. The apparatus of claim 7,

wherein the delay element is a digitally programmable device configured to adjust a rising edge of the filtered signal using a control signal from the digital filter.

9. The apparatus of claim 7,

wherein the delay element and the digital filter are further configured to reduce the portion of the amount of PLL noise after the PLL device enters a steady-state mode.

10. The apparatus of claim 7,

wherein the first digital phase detector is a Godard digital phase detector, and

wherein the transmitter clock signal is extracted from a received signal using Godard binning.

11. The apparatus of claim 7,

wherein the transmitter clock signal is extracted from a serializer-deserializer (SerDes) input signal.

12. The apparatus of claim 7,

wherein the phase rotator decouples a clock recovery bandwidth from a bandwidth of the PLL device.

13. The apparatus of claim 7,

wherein the output signal is a receiver clock signal within a transceiver.

14. A receiver apparatus, comprising:

a phase locked loop (PLL) device that includes

an analog phase detector configured to obtain a reference signal, and

a voltage-controlled oscillator (VCO) device, wherein the VCO device is configured to generate, based on the reference signal, an output signal;

a phase rotator coupled to the VCO device and the analog phase detector;

a digital phase detector coupled to the VCO device, the digital phase detector being configured to determine an amount of phase difference between a transmitter clock signal and the output signal;

a digital accumulator coupled to the digital phase detector, wherein the phase rotator and the digital accumulator are configured, using the amount of phase difference between the transmitter clock signal and the output signal, to filter a portion of the amount of phase difference from the output signal to generate a filtered signal for transmission to the analog phase detector;

a reference clock source configured to generate the reference signal; and

a frequency counter coupled to the VCO device and the reference clock source,

wherein the frequency counter is configured to determine a frequency difference between a frequency of the reference clock source and a frequency of the VCO device, and

wherein the frequency counter is further configured to generate a control signal configured to change the frequency of the reference clock source based on the frequency difference.

15. The apparatus of claim 14,

wherein the reference clock source is a crystal oscillator.

16. The apparatus of claim 14,

wherein the frequency counter is further configured to reduce a frequency difference between a receiver clock signal from the reference clock source and a transmitter clock signal to be within a predetermined margin.

17. The apparatus of claim 14,

wherein the digital phase detector is a Godard digital phase detector, and

wherein the transmitter clock signal is extracted from an optical signal using Godard binning.

18. The apparatus of claim 14,

wherein the transmitter clock signal is extracted from a serializer-deserializer (SerDes) input signal.

19. The apparatus of claim 14,

wherein the phase rotator decouples a clock recovery bandwidth from a bandwidth of the PLL device.

20. The apparatus of claim 14,

wherein the output signal is a receiver clock signal within a transceiver.