Systems and methods for selectively addressing sparsely arranged electronic measurement devices

• US 10,190,158 B2
• Filed: 08/03/2016
• Issued: 01/29/2019
• Est. Priority Date: 08/06/2015
• Status: Active Grant

• Current Assignee: Pacific Bioscience of California Incorporated (L'Oreal SA)
• Original Assignee: Pacific Bioscience of California Incorporated (L'Oreal SA)
• Inventors: Turner, Stephen, Korlach, Jonas, Warren, Steven
• Primary Examiner(s): Toatley, Jr., Gregory J
• Assistant Examiner(s): Dinh, Lynda
• Application Number:
  US15/227,357
• Publication Number:
  US 20170038333A1
• Time in Patent Office: 909 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 15/00 Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: C12Q 1/6874 involving nucleic acid arrays, e.g. sequencing by hybridisation
• CPC Class Codes: C12Q 2521/101 DNA polymerase
• CPC Class Codes: C12Q 2525/197 incorporating a spacer/coupling moiety
• CPC Class Codes: C12Q 2533/101 Primer extension
• CPC Class Codes: C12Q 2537/157 A reaction step characterised by the number of molecules incorporated or released
• CPC Class Codes: C12Q 2563/116 electrical properties of nucleic acids, e.g. impedance, conductivity or resistance
• CPC Class Codes: C12Q 2565/301 Pyrophosphate (PPi)
• CPC Class Codes: C12Q 2565/607 being a sensor, e.g. electrode
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4146 involving nanosized elements, e.g. nanotubes, nanowires
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1606 Graphene

Abstract

A circuit comprising a substrate with sectors on the substrate is provided, each sector comprising clock and data lines, a controller in electrical communication with the clock and data lines, a counter bias line, an amplifier input line and nano-electronic measurement devices on the substrate. A source of each device is coupled to the counter bias line and a drain of each device is coupled to the amplifier input line to obtain an electrical signal on the drain, the identity of which is determined by electrical interaction between the device and a charge label. Each device drain is gated by a corresponding switch between an on state, in which the drain is connected to the amplifier input line, and an off state, in which the drain is isolated from the amplifier input line. The controller controls switch states responsive to clock signal line pulses and data input line data.

Claims

1. An integrated circuit comprising:

a substrate;

a plurality of sectors arranged on the substrate, wherein each sector in the plurality of sectors comprises;

a programmable switch controller;

a counter bias line;

an amplifier input line;

a plurality of nano-electronic measurement devices spatially arranged on the substrate, wherein

each respective nano-electronic measurement device in the plurality of nano-electronic measurement devices includes a source that is coupled to the counter bias line and a drain that is coupled to the amplifier input line thereby obtaining an electrical signal on the drain of the respective nano-electronic measurement device,

the electrical signal is any one of a discrete set of electrical signals,

an identity of the electrical signal in the discrete set of electrical signals is determined by an electrical interaction between the corresponding nano-electronic measurement device and a particular charge label in a plurality of charge labels; and

a plurality of switches, wherein each switch in the plurality of switches gates the electrical signal between the drain of a corresponding nano-electronic measurement device in the plurality of nano-electronic measurement devices and the amplifier input line between

(i) an on state, in which the electrical signal at the drain of the corresponding nano-electronic measurement device is delivered to the amplifier input line, and

(ii) an off state, in which the electrical signal at the drain of the corresponding nano-electronic measurement device is not delivered to the amplifier input line, wherein

each respective switch in the plurality of switches is independently wired to the programmable switch controller thereby causing the respective switch to be in one of the on state and the off state responsive to the programmable switch controller.

2. The integrated circuit of claim 1, further comprising:

a first clock signal line and a data input line, and wherein

the programmable switch controller of a sector in the plurality of sectors comprises a first shift register comprising a first plurality of flip-flops in electrical communication with the first clock signal line, wherein

the first plurality of flip-flops comprises an initial flip-flop and a terminal flip-flop,

each flip-flop includes a serial input and a serial output, wherein the serial output of each respective flip-flop in the first plurality of flip-flops, other than the terminal flip-flop, is uniquely electrically connected to the serial input of another flip-flop in the first plurality of flip-flops, thereby electrically coupling the first plurality of flip-flops in series,

the serial input of the initial flip-flop is electrically connected to the data input line, wherein the first shift register is configured to receive a device scan chain sequence, from the data input line, that is propagated through the first plurality of flip-flops by electrical pulses in the first clock signal line thereby independently biasing each flip-flop in the first plurality of flip-flops to one of a first state and a second state; and

each respective switch in the plurality of switches is independently wired to the programmable switch controller through a corresponding flip-flop in the first plurality of flip-flops thereby causing the respective switch to be in the off state when the corresponding flip-flop is biased to the first state and causing the respective switch to be in the on state when the corresponding flip-flop is biased to the second state.

3. The integrated circuit of claim 2, wherein the sector in the plurality of sectors further comprises:

a shunt scan chain input line; and

a shunt clock signal line;

the programmable switch controller further comprises a second shift register comprising a second plurality of flip-flops in electrical communication with the shunt clock signal line, wherein

the second plurality of flip-flops comprises an initial flip-flop and a terminal flip flop,

each flip-flop in the second plurality of flip-flops includes a serial input and a serial output, wherein the serial output of each flip-flop in the second plurality of flip-flops, other than the terminal flip-flop, is uniquely electrically connected to the serial input of another flip-flop in the second plurality of flip-flops, thereby electrically coupling the second plurality of flip-flops in series,

the serial input of the initial flip-flop in the second plurality of flip-flops is electrically connected to the shunt scan chain input line, wherein the second shift register is configured to receive a shunt scan chain sequence that is propagated through the second plurality of flip-flops by electrical pulses in the shunt clock signal line, thereby independently biasing each flip-flop in the second plurality of flip-flops to one of a third state and a forth state;

the programmable switch controller further comprises a plurality of multiplexers, wherein each multiplexer in the plurality of multiplexers includes a first input line, a second input line, a select line, and an output line, wherein

the first input line of each respective multiplexer in the plurality of multiplexers is in electrical communication with the serial output of a first corresponding flip-flop in the first plurality of flip-flops,

the second input line of each respective multiplexer in the plurality of multiplexers is in electrical communication with the serial input of the first corresponding flip-flop in the first plurality of flip-flops,

the select line of each respective multiplexer in the plurality of multiplexers is in electrical communication with the serial output of a first corresponding flip-flop in the second plurality of flip-flops, and

the output line of each respective multiplexer in the plurality of multiplexers is in electrical communication with the serial input of a second corresponding flip-flop in the first plurality of flip-flops; and

a first plurality of AND gates, wherein each AND gate in the first plurality of AND gates comprises an output, a first input and a second input, wherein

the first input of each respective AND gate in the first plurality of AND gates is in electrical communication with the first clock signal line,

the second input of each respective AND gate in the first plurality of AND gates is in electrical communication with the serial output of the first corresponding flip-flop in the second plurality of flip-flops, and

each respective flip-flop in the first plurality of flip-flops is in electrical communication with the first clock signal line through the output of a corresponding AND gate in the first plurality of AND gates, wherein

when a respective flip-flop in the second plurality of flip-flops, that is in electrical communication with the second input of the respective AND gate, is in the third state, the first clock signal line is not applied to the respective flip-flop in the first plurality of flip-flops and the select line of the multiplexer in the plurality of multiplexers that is in electrical communication with the output of the respective flip-flop in the second plurality of flip-flops is biased to the second input line of the respective multiplexer, and

when the flip-flop in the second plurality of flip-flops, that is in electrical communication with the second input of the respective AND gate, is in the fourth state, the first clock signal line is applied to the respective flip-flop in the first plurality of flip-flops and the select line of the multiplexer in the plurality of multiplexers that is in electrical communication with the output of the respective flip-flop in the second plurality of flip-flops is biased to the first input line of the respective multiplexer.

4. The integrated circuit of claim 3, wherein the output line of each respective multiplexer in the plurality of multiplexers is in electrical communication with the serial input of a second corresponding flip-flop in the first plurality of flip-flops through a corresponding buffer gate in a plurality of buffer gates.

5. The integrated circuit of claim 3, wherein

each flip-flop in the first plurality of flip-flops further comprises a first reset;

each flip-flop in the second plurality of flip-flops further comprises a second reset;

the sector further comprises a shunt signal line; and

the programmable switch controller further comprises a second plurality of AND gates, wherein each AND gate in the second plurality of AND gates has an output, a first input and a second input, wherein

the first input of each respective AND gate in the second plurality of AND gates is in electrical communication with the serial output of a first flip-flop in the first plurality of flip-flops,

the second input of each respective AND gate in the second plurality of AND gates is in electrical communication with the shunt signal line, and

the output of each respective AND gate in the second plurality of AND gates is in electrical communication with the first reset of the corresponding flip-flop in the first plurality of flip-flops and the second reset of a corresponding flip-flop in the second plurality of flip-flops, thereby causing the first corresponding flip-flop to reset to the first state and the second corresponding flip-flop to reset to the third state when the shunt signal line is asserted at the same time that the data input line drives the corresponding flip-flop in the first plurality of flip-flop to the second state.

6. The integrated circuit of claim 2, wherein the data input line is configured to receive instructions that permanently by-pass more than fifty percent of the devices in the plurality of devices in a sector in the plurality of sectors.

7. The integrated circuit of claim 6, wherein the plurality of sectors comprises ten or more sectors and the plurality of nano-electronic measurement devices in each sector in the plurality of sectors comprises one hundred devices.

8. The integrated circuit of claim 2, wherein the integrated circuit is configured to receive signals on the data input line that permanently bypass fifty percent or more of the nano-electronic measurement devices in a sector in the plurality of sectors thereby permanently causing bypassed nano-electronic measurement devices to be in the off state.

9. The integrated circuit of claim 2, wherein the integrated circuit is configured to receive signals on the data input line that permanently bypass eighty percent or more of the nano-electronic measurement devices in a sector in the plurality of sectors thereby permanently causing bypassed nano-electronic measurement devices to be in the off state.

10. The integrated circuit of claim 1, wherein

the programmable switch controller of a sector in the plurality of sectors comprises:

a memory controller,

a memory in electrical communication with the memory controller,

a column decoder in electrical communication with the memory, and

a row decoder in electrical communication with the memory;

and wherein the sector further comprises;

a plurality of AND gates, wherein each AND gate in the plurality of AND gates comprises an output, a first input and a second input, wherein

the first input of each respective AND gate in the plurality of AND gates is in electrical communication with the column decoder,

the second input of each respective AND gate in the plurality of AND gates is in electrical communication with the row decoder, and

each respective switch in the plurality of switches is independently wired to the programmable switch controller through the output of a corresponding AND gate in the plurality of AND gates, thereby causing the respective switch to be in the on state when the row decoder and the column decoder both signal a first state to the respective switch and otherwise causing the respective switch to be in the off state.

11. The integrated circuit of claim 1, wherein

the sector further comprises a first clock line, a data input line, a second clock line, and a restart scan chain line;

the programmable switch controller of a sector in the plurality of sectors comprises;

a row shift register comprising a first plurality of flip-flops, wherein an initial flip-flop in the first plurality of flip-flops is in electrical communication with the data input line and the first clock signal line;

a plurality of AND gates, each AND gate in the plurality of AND gates comprising a first input, a second input and an output, and

a plurality of column shift registers, each column shift register comprising a second plurality of flip-flops, and wherein

the first input of each AND gate in the plurality of AND gates is in electrical communication with an output of a corresponding flip-flop in the first plurality of flip-flops of the row shift register;

the second input of each AND gate in the plurality of AND gates is in electrical communication with the second clock line,

the respective second plurality of flip-flops of each respective column shift register in the plurality of column shift registers comprises an initial flip-flop and a terminal flip-flop,

each flip-flop in the respective second plurality of flip-flops includes a serial data input, a clock pulse input, and a serial data output,

the serial data output of each respective flip-flop in the second plurality of flip-flops, other than the terminal flip-flop, is uniquely electrically connected to the serial data input of another flip-flop in the second plurality of flip-flops, thereby electrically coupling the second plurality of flip-flops in series,

the clock pulse input of each flip-flop in the second plurality of flip-flops is electrically connected to the output of an AND gate in the first plurality of AND gates,

each respective column shift register in the plurality of column shift registers is configured to receive a logical “

1”

or “

0”

from the restart scan chain line that is propagated from the initial flip-flop in the second plurality of flip-flops through the second plurality of flip-flops by electrical pulses received at the clock pulse input of each respective flip-flop in the second plurality of flip-flops thereby independently biasing each flip-flop in the second plurality of flip-flops to one of the first state and the second state,

each respective switch in the plurality of switches is independently wired to the programmable switch controller through the output of a corresponding flip-flop in the second plurality of flip-flops of a corresponding column shift register, thereby causing the respective switch to;

be in the off state when the corresponding flip-flop in the second plurality of flip-flops of the corresponding column shift register is biased to a first state, and

be in the on state when the corresponding flip-flop in the second plurality of flip-flops of the corresponding column shift register is biased to the second state.

12. The integrated circuit of claim 1, wherein

the sector further comprises a first clock line, a data input line, a second clock line, a load buffer line, and a restart scan chain line,

the programmable switch controller of a sector in the plurality of sectors comprises:

a row shift register comprising a first plurality of flip-flops, wherein an initial flip-flop in the first plurality of flip-flops is in electrical communication with the data input line and the first clock signal line;

a plurality of AND gates, each AND gate in the plurality of AND gates comprising a first input, a second input, and an output, and

a plurality of column shift registers, each column shift register comprising a second plurality of flip-flops and a third plurality of flip-flops, and wherein

the first input of each AND gate in the first plurality of AND gates is in electrical communication with an output of a corresponding flip-flop in the first plurality of flip-flops of the row shift register;

the second input of each AND gate in the first plurality of AND gates is in electrical communication with the second clock line,

the respective second plurality of flip-flops of each respective column shift register in the plurality of column shift registers comprises an initial flip-flop and a terminal flip-flop,

each flip-flop in the respective second plurality of flip-flops includes a serial data input, a clock pulse input, and a serial data output,

the serial data output of each respective flip-flop in the second plurality of flip-flops, other than the terminal flip-flop, is uniquely electrically connected to the serial data input of another flip-flop in the second plurality of flip-flops, thereby electrically coupling the second plurality of flip-flops in series,

the clock pulse input of each flip-flop in the second plurality of flip-flops is electrically connected to the output of an AND gate in the first plurality of AND gates,

each respective column shift register in the plurality of column shift registers is configured to receive a logical “

1”

or “

0”

from the restart scan chain line that is propagated from the initial flip-flop in the second plurality of flip-flops through the second plurality of flip-flops by electrical pulses received at the clock pulse input of each respective flip-flop in the second plurality of flip-flops thereby independently biasing each flip-flop in the second plurality of flip-flops to one of the first state and the second state,

each respective flip-flop in the third plurality of flip-flops comprises a data input, a data output and a clock pulse input, and wherein

the clock pulse input of each respective flip-flop in the third plurality of flip-flops is electrically connected to the load buffer line,

the data input of each respective flip-flop gate in the third plurality of flip-flops is wired to the output of a corresponding flip-flop in the second plurality of flip-flops, thereby causing the state of the corresponding flip-flop in the third plurality of flip-flops to be biased to the first state when the corresponding flip-flip in the second plurality of flip-flops is biased to the first state and the load buffer line is asserted, and the state of the corresponding flip-flop in the third plurality of flip-flops to be biased to the second state when the corresponding flip-flip in the second plurality of flip-flops is biased to the second state and the load buffer line is asserted,

each respective switch in the plurality of switches is independently wired to the programmable switch controller through the output of a corresponding flip-flop in the third plurality of flip-flops of a corresponding column shift register, thereby causing the respective switch to

be in the off state when the corresponding flip-flop in the third plurality of flip-flops of the corresponding column shift register is biased to the first state, and

be in the on state when the corresponding flip-flop in the third plurality of flip-flops of the corresponding column shift register is biased to the second state.

13. The integrated circuit of claim 1, wherein a nano-electronic measurement device in the plurality of nano-electronic measurement devices is a nanoFET that comprises the source, the drain, a gate, and a channel and wherein the input from the counter bias line is applied from the source to the drain across the channel.

14. The integrated circuit of claim 13, wherein the channel is a nanowire, a carbon nanotube, or a graphene nanoribbon.

15. The integrated circuit of claim 13, wherein the channel is a nanopore.

16. The integrated circuit of claim 1, wherein the counter bias line carries a DC voltage and the application of the counter bias line to the nano-electronic measurement device results in a DC current in the channel nano-electronic measurement device.

17. The integrated circuit of claim 1, wherein the counter bias line carries an AC voltage and a frequency of the AC voltage is changed with time during application of the counter bias line to the nano-electronic measurement device.

18. The integrated circuit of claim 1, wherein each charge label in the plurality of charge labels represents a different type of nucleotide analog in a plurality of nucleotide analogs.

19. The integrated circuit of claim 18, wherein a polymerase enzyme is attached to the corresponding nano-electronic measurement device and the particular charge label that forms an electrical interaction with the corresponding nano-electronic measurement device is freed from a corresponding nucleotide analog in the plurality of nucleotide analogs by the polymerase enzyme as part of a polymerase mediated nucleic acid synthesis reaction with a template nucleic acid.

20. The integrated circuit of claim 19, wherein a charge label in the plurality of charge labels comprises a protein.

21. The integrated circuit of claim 20, wherein the protein has a molecular weight that is between 1/10 and 3 times the molecular weight of the polymerase enzyme.

22. The integrated circuit of claim 20, wherein the protein has a molecular weight that is between 1/10 and 3 times the molecular weight of a phi29 polymerase.

23. The integrated circuit of claim 1, wherein at least one of the charge labels in the plurality of charge labels comprises a polymer chain characterized by multiple charges.

24. The integrated circuit of claim 1, wherein each charge label in the plurality of charge labels comprises a polymer chain characterized by a unique net positive or negative charge.

25. The integrated circuit of claim 1, wherein

a first charge label in the plurality of charge labels comprises a first polymer chain having a unique net positive charge, and

a second charge label in the plurality of charge labels comprises a second polymer chain having a unique net negative charge.

26. The integrated circuit of claim 1, wherein the plurality of nano-electronic measurement devices of a sector in the plurality of sectors are arranged as a row or a column on the substrate.

27. The integrated circuit of claim 1, wherein the plurality of nano-electronic measurement devices of a sector in the plurality of sectors are arranged as a plurality of rows or a plurality of columns on the substrate.

28. The integrated circuit of claim 1, further comprising a plurality of amplifiers, wherein each amplifier in the plurality of amplifiers is in electrical communication with the amplifier input line of a corresponding sector in the plurality of sectors.

29. The integrated circuit of claim 28, wherein an amplifier in the plurality of amplifiers is a current-to-voltage amplifier.

30. The integrated circuit of claim 1, wherein the electrical interaction is electrostatic.

31. The integrated circuit of claim 1, wherein the plurality of nano-electronic measurement devices comprises 1,000 nano-electronic measurement devices.

32. The integrated circuit of claim 1, wherein the plurality of nano-electronic measurement devices comprises 10,000 nano-electronic measurement devices.

33. The integrated circuit of claim 1, wherein the plurality of nano-electronic measurement devices consists of between 1,000 nano-electronic measurement devices and 10 million nano-electronic measurement devices.

34. The integrated circuit of claim 1, wherein the plurality of measurement devices consists of between 10,000 nano-electronic measurement devices and 1 million nano-electronic measurement devices.

35. The integrated circuit of claim 1, wherein

only a single nano-electronic measurement device in the plurality of nano-electronic measurement devices in each sector in the plurality of sectors is in the on state at a given point in time, and

the plurality of nano-electronic measurement devices of each sector in the plurality of sectors comprises three hundred devices.

36. The integrated circuit of claim 1, wherein the plurality of sectors comprises one hundred sectors and the plurality of nano-electronic measurement devices in each sector in the plurality of sectors comprises one thousand devices.