Configuring power management functionality in a processor

• US 10,191,532 B2
• Filed: 02/19/2016
• Issued: 01/29/2019
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bhandaru, Malini K., Dehaemer, Eric J., Bobholz, Scott P., Makaram, Raghunandan, Garg, Vivek
• Primary Examiner(s): Suryawanshi, Suresh
• Application Number:
  US15/048,055
• Publication Number:
  US 20160170478A1
• Time in Patent Office: 1,075 Days
• Field of Search: 713320
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

Claims

1. A system comprising:

a plurality of processors;

a processor interconnect to communicatively couple two or more of the plurality of processors;

a system memory comprising a dynamic random access memory communicatively coupled to one or more of the plurality of processors over a memory interconnect;

at least one of the plurality of processors comprising;

a plurality of cores formed on a single semiconductor die, a core of the plurality of cores to execute one or more threads;

the core of the plurality of cores comprising a fetch unit to fetch instructions from an instruction cache, a decode unit to decode the instructions and a plurality of execution units to perform out-of-order execution of the instructions;

one or more control registers to store a first indication that two or more cores of the plurality of cores are to operate at independent performance states comprising active power states in which the two or more cores are to operate at different frequencies and a second indication that a first set of cores are to operate at a common performance state comprising an active power state in which the first set of cores are to operate at a common frequency;

a plurality of voltage regulators formed on the single semiconductor die, a voltage regulator of the plurality of voltage regulators associated with one of the plurality of cores;

a power controller formed on the single semiconductor die, the power controller to control the plurality of voltage regulators to provide a voltage and/or frequency to a first core of the plurality of cores independently of a voltage and/or frequency to one or more other cores and to determine whether to update the voltage and/or frequency of the first core based on a workload of the first core, thermal constraints, and activity counters; and

at least one additional voltage regulator formed on the single semiconductor die and associated with processor circuitry external to the plurality of cores, the at least one additional voltage regulator to allow the processor circuitry external to the plurality of cores to operate at a different voltage and/or frequency than one or more cores of the plurality of cores.

2. The system of claim 1, further comprising at least one data communication device communicatively coupled to at least one of the plurality of processors.

3. The system of claim 1, further comprising at least one storage device communicatively coupled to at least one of the plurality of processors.

4. The system of claim 1, wherein the at least one of the plurality of processors comprises a cache shared by two or more of the plurality of cores.

5. The system of claim 1, further comprising an audio device communicatively coupled to at least one of the plurality of processors.

6. The system of claim 1, wherein the system comprises a mobile device.

7. The system of claim 1, wherein the system comprises a tablet computer.

8. The system of claim 1, wherein the core of the plurality of cores is to execute at a performance state most recently requested by a thread that is to execute on the core.

9. The system of claim 1, wherein the core of the plurality of cores is to execute at a performance state corresponding to a maximum performance state of a plurality of performance states requested by a plurality of threads that are to execute on the core.

10. The system of claim 1, wherein in a first power management mode the core of the plurality of cores is to execute at a performance state most recently requested by a thread that is to execute on the core, and in a second power management mode the core is to execute at a performance state corresponding to a maximum performance state of a plurality of performance states requested by one of a plurality of threads that are to execute on the core.

11. The system of claim 1, wherein the at least one of the plurality of processors is to update the one or more control registers in a secure mode of operation.

12. The system of claim 1, wherein the power controller is to communicatively couple to the plurality of cores by a plurality of interconnections.

13. The system of claim 12, wherein the plurality of interconnections comprises bi-directional interconnections.

14. The system of claim 1, wherein the at least one of the plurality of processors comprises at least one traffic sensor to store at least one traffic measurement.

15. The system of claim 1, wherein the core of the plurality of cores further comprises a retirement unit to retire the instructions.

16. The system of claim 1, wherein the plurality of execution units comprises a single instruction multiple data unit.

17. The system of claim 16, wherein the plurality of execution units further comprises an arithmetic logic unit.

18. The system of claim 1, wherein the second indication comprises a single power domain indicator to indicate whether the first set of cores are to be treated as a single power domain to operate at the common performance state.