Enhanced address space layout randomization

• US 10,191,791 B2
• Filed: 07/02/2016
• Issued: 01/29/2019
• Est. Priority Date: 07/02/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Stark, Tomer, Gabor, Ron, Nuzman, Joseph
• Primary Examiner(s): Manoskey, Joseph D
• Application Number:
  US15/201,443
• Publication Number:
  US 20180004445A1
• Time in Patent Office: 941 Days
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/657 Virtual address space management

Abstract

One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.

Claims

1. An enhanced address space layout randomization apparatus comprising:

a linear address space comprising a metadata data structure;

metadata logic to generate a metadata value; and

enhanced address space layout randomization (ASLR) logic to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address,

the address pointer corresponding to an apparent address in an enhanced address space, a size of the enhanced address space greater than a size of the linear address space.

2. The apparatus of claim 1, further comprising memory corruption detection (MCD) logic to compare a target metadata value in a target address pointer comprising the linear address to the metadata value stored to the metadata data structure and to generate a fault if the target metadata value and the stored metadata value are not the same.

3. The apparatus of claim 1, wherein the metadata data structure is a two level data structure.

4. The apparatus of claim 1, wherein the metadata value is included in one or more upper bits of the address pointer.

5. The apparatus of claim 1, wherein the metadata value is a random number.

6. The apparatus of claim 1, wherein the linear address comprises 48 bits and the address pointer comprises 64 bits.

7. The apparatus of claim 1, wherein the metadata data structure comprises a metadata directory and a metadata table.

8. An enhanced address space layout randomization method comprising:

generating, by metadata logic, a metadata value;

combining, by enhanced address space layout randomization (ASLR) logic, the metadata value and a linear address into an address pointer; and

storing, by the enhanced ASLR logic, the metadata value to a metadata data structure at a location pointed to by a least a portion of the linear address,

the metadata data structure being included in a linear address space, the address pointer corresponding to an apparent address in an enhanced address space having a size that is greater than a size of the linear address space.

9. The method of claim 8, further comprising comparing, by memory corruption detection (MCD) logic, a target metadata value in a target address pointer comprising the linear address to the metadata value stored to the metadata data structure;

and generating, by the MCD logic, a fault if the target metadata value and the stored metadata value do not match.

10. The method of claim 8, wherein the metadata data structure is a two level data structure.

11. The method of claim 8, wherein the metadata value is included in one or more upper bits of the address pointer.

12. The method of claim 8, wherein the metadata value is a random number.

13. The method of claim 8, wherein the linear address comprises 48 bits and the address pointer comprises 64 bits.

14. The method of claim 8, wherein the metadata data structure comprises a metadata directory and a metadata table.

15. An enhanced address space layout randomization system comprising:

a processor comprising at least one processor register;

a linear address space comprising a metadata data structure;

metadata logic to generate a metadata value; and

enhanced address space layout randomization (ASLR) logic to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address,

the address pointer corresponding to an apparent address in an enhanced address space, a size of the enhanced address space greater than a size of the linear address space.

16. The system of claim 15, further comprising memory corruption detection (MCD) logic to compare a target metadata value in a target address pointer comprising the linear address to the metadata value stored to the metadata data structure and to generate a fault if the target metadata value and the stored metadata value do not match.

17. The system of claim 15, wherein the metadata data structure is a two level data structure.

18. The system of claim 15, wherein the metadata value is included in one or more upper bits of the address pointer.

19. The system of claim 15, wherein the metadata value is a random number.

20. The system of claim 15, wherein the linear address comprises 48 bits and the address pointer comprises 64 bits.

21. The system of claim 15, wherein the metadata data structure comprises a metadata directory and a metadata table.

22. The system of claim 15, wherein the at least one processor register is to store a metadata base pointer.

23. A computer readable storage device having stored thereon instructions that when executed by one or more processors result in the following operations comprising:

generating a metadata value;

combining the metadata value and a linear address into an address pointer; and

storing the metadata value to a metadata data structure at a location pointed to by a least a portion of the linear address,

the metadata data structure included in a linear address space, the address pointer corresponding to an apparent address in an enhanced address space that is larger than the linear address space.

24. The device of claim 23, wherein the instructions that when executed by one or more processors results in additional operations comprising:

comparing a target metadata value in a target address pointer comprising the linear address to the metadata value stored to the metadata data structure; and

generating a fault if the target metadata value and the stored metadata value do not match.

25. The device of claim 23, wherein the metadata data structure is a two level data structure.