Host device, access system, and access method

• US 10,191,841 B2
• Filed: 07/05/2016
• Issued: 01/29/2019
• Est. Priority Date: 07/06/2015
• Status: Active Grant

• Current Assignee: Shannon Systems Ltd.
• Original Assignee: Shannon Systems Ltd.
• Inventors: Yang, Xueshi, Miao, Ningzhong
• Primary Examiner(s): Mercado, Ramon A.
• Application Number:
  US15/202,091
• Publication Number:
  US 20170010962A1
• Time in Patent Office: 938 Days
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/262 configured as RAID
• CPC Class Codes: G06F 2212/403 Error protection encoding, e.g. using parity or ECC codes
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A host device is provided. The host device includes a processor and an interface. The processor generates a physical block address and a solid state disk (SSD) identification code according to a logical block address of an access operation. The interface is coupled to the processor. The processor indicates one of a plurality of SSDs through the interface according to the SSD identification code to access data at the physical block address.

Claims

1. A host device comprising:

a storage device storing a physical mapping table;

a processor checking the physical mapping table according to a first logical block address and a second logical block address of an access operation to find a first physical block address, a second physical block address, a first solid state disk (SSD) identification code, and a second SSD identification code; and

an interface, coupled to the processor,

wherein the processor transmits the first physical block address which is found from the physical mapping table to one of a plurality of SSDs through the interface according to the first SSD identification code to access data at the first physical block address and transmits the second physical block address which is found from the physical mapping table to another one of the plurality of SSDs through the interface according to the second SSD identification code to access a horizontal parity code at the second physical block address,

wherein the plurality of SSDs are disposed outside of the processor,

wherein the plurality of SSDs form a redundant array of independent disks (RAID), and the RAID stores the data into a first SSD among the plurality of SSDs and further stores the horizontal parity code and a vertical parity code which correspond to the data respectively into a second SSD and a third SSD among the plurality of SSDs, and

wherein the processor generates the horizontal parity code and the vertical parity code according to the data and checks or recovers the data according to the horizontal parity code and the vertical parity code.

2. The host device as claimed in claim 1, wherein the interface is a serial advanced technology attachment (SATA) interface or a peripheral component interconnect express (PCIe) interface.

3. The host device as claimed in claim 1, wherein the RAID further stores a depth parity code.

4. The host device as claimed in claim 3, wherein the processor generates the depth parity code according to the horizontal parity code or the vertical parity code.

5. The host device as claimed in claim 1,

wherein the physical mapping table comprises the first and second logical block addresses, the first and second physical block addresses, and relationship information concerning the first and second logical block addresses and the first and second physical block addresses.

6. The host device as claimed in claim 1, wherein the processor accesses one of the data, the horizontal parity code, and the vertical parity code according to the SSD identification code.

7. The host device as claimed in claim 1, wherein the processor maintains a flash translation layer (FTL) to record mapping between the first and second logical block addresses and the first and second physical block addresses.

8. The host device as claimed in claim 7, wherein the mapping between the first and second logical block addresses and the first and second physical block addresses is recorded into the physical mapping table.

9. An access system comprising:

a host device comprising;

a storage device storing a physical mapping table;

a processor checking the physical mapping table according to a first logical block address and a second logical block address of an access operation to find a first physical block address, a second physical block address, a first solid state disk (SSD) identification code, and a second SSD identification code; and

an interface, coupled to the processor; and

a plurality of SSDs coupled to the interface and disposed outside of the host,

wherein the processor transmits the first physical block address which is found from the physical mapping table to a first SSD among the plurality of SSDs through the interface according to the first SSD identification code to access data at the physical block address and transmits the second physical block address which is found from the physical mapping table to a second SSD among the plurality of SSDs through the interface according to the second SSD identification code to access a horizontal parity code at the second physical block address,

wherein the plurality of SSDs form a redundant array of independent disks (RAID), and the RAID stores the data into the first SSD and further stores the horizontal parity code and a vertical parity code which correspond to the data respectively into a second SSD and a third SSD among the plurality of SSDs, and

wherein the processor generates the horizontal parity code and the vertical parity code according to the data and checks or recovers the data according to the horizontal parity code and the vertical parity code.

10. The access system as claimed in claim 9, wherein the interface is a serial advanced technology attachment (SATA) interface or a peripheral component interconnect express (PCIe) interface.

11. The access system as claimed in claim 9, wherein the RAID further stores a depth parity code.

12. The access system as claimed in claim 11, wherein the processor generates the depth parity code according to the horizontal parity code or the vertical parity code.

13. The access system as claimed in claim 9, wherein the physical mapping table comprises the first and second logical block addresses, the first and second physical block addresses, and relationship information concerning the first and second logical block addresses and the first and second physical block addresses.

14. The access system as claimed in claim 9, wherein the processor accesses one of the data, the horizontal parity code, and the vertical parity code according to the SSD identification code.

15. The access system as claimed in claim 9, wherein the processor maintains a flash translation layer (FTL) to record mapping between the first and second logical block addresses and the first and second physical block addresses.

16. The access system as claimed in claim 15, wherein the mapping between the first and second logical block addresses and the first and second physical block addresses is recorded into the physical mapping table.

17. An access method comprising:

storing a mapping table in a storage device of a host device;

checking, by a processor of the host device, the physical mapping table according to a first logical block address and a second logical block address of an access operation to find a first physical block address, a second physical block address, a first solid state disk (SSD) identification code, and a second SSD identification code;

transmitting, by the processor, the first physical block address which is found from the physical mapping table to one of a plurality of SSDs through the interface according to the first SSD identification code;

transmitting, by the processor, the second physical block address which is found from the physical mapping table to another one of the plurality of SSDs through the interface according to the second SSD identification code;

accessing, by the one of the plurality of SSDs, data at the first physical block address,

accessing, by the another one of the plurality of SSDs, a horizontal parity code at the second physical block address; and

generating, by the processor, the horizontal parity code and a vertical parity code according to the data,

wherein the plurality of SSDs form a redundant array of independent disks (RAID), and the access method further comprises;

storing the data into a first SSD among the plurality of SSDs;

storing the horizontal parity code and the vertical parity code which correspond to the data respectively into a second SSD and a third SSD among the plurality of SSDs; and

recovering, by the first processor, the data according to the horizontal parity code and the vertical parity code when the first SSD is broken.

18. The access system as claimed in claim 17, wherein the interface is a serial advanced technology attachment (SATA) interface or a peripheral component interconnect express (PCIe) interface.

19. The access system as claimed in claim 17, further comprising:

storing a depth parity code into the RAID.

20. The access method as claimed in claim 19, further comprising:

generating, by the processor, the depth parity code according to the horizontal parity code or the vertical parity code.

21. The access system as claimed in claim 17, wherein the physical mapping table comprises the first and second logical block addresses, the first and second physical block addresses, and relationship information concerning the first and second logical block addresses and the first and second physical block addresses.

22. The access method as claimed in claim 17, further comprising:

accessing, by the processor, one of the data, the horizontal parity code, and the vertical parity code according to the SSD identification code.

23. The access method as claimed in claim 17, wherein a flash translation layer (FTL) is maintained in the processor to record mapping between the first and second logical block addresses and the first and second physical block addresses.

24. The access method as claimed in claim 23, wherein the mapping between the first and second logical block addresses and the first and second physical block addresses is recorded into the physical mapping table.