Unaligned data coalescing

• US 10,191,843 B2
• Filed: 02/15/2018
• Issued: 01/29/2019
• Est. Priority Date: 07/01/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Palmer, David A.
• Primary Examiner(s): Sadler, Nathan
• Application Number:
  US15/897,797
• Publication Number:
  US 20180173621A1
• Time in Patent Office: 348 Days
• Field of Search: 711103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure includes methods and systems for coalescing unaligned data. One method includes receiving a first write command associated with a first unaligned portion of data, receiving a second write command associated with a second unaligned portion of data, and coalescing the first unaligned portion of data and the second unaligned portion of data, wherein coalescing includes writing the first unaligned portion of data and the second unaligned portion of data to a page in a memory device.

Claims

1. A method for unaligned data coalescing, comprising:

receiving a first write command associated with an unaligned portion of data; and

coalescing, using a coalescing tree, the unaligned portion of data with data associated with another write command, wherein a logical address of the unaligned portion of data and a logical address of the data associated with the another write command correspond to a particular logical page.

2. The method of claim 1, further including creating a first indicator corresponding to the data from the another write command, wherein the first indicator refers to the logical address of the data associated with the another write command and the particular logical page.

3. The method of claim 1, further including creating a second indicator corresponding to the unaligned portion of data, wherein the second indicator refers to the logical address of the unaligned portion of data and the particular logical page.

4. The method of claim 1, further including comparing a first indicator corresponding to the data from the another write command to a second indicator corresponding to the unaligned portion of data.

5. The method of claim 4, further including coalescing the unaligned portion of data with the data associated with another write command responsive to the first indicator and the second indicator referring to the particular logical page.

6. The method of claim 1, further including storing the unaligned portion of data and the data associated with another write command in a buffer on a controller during coalescing.

7. A method for unaligned data coalescing, comprising:

receiving a write command associated with a first unaligned portion of data and an aligned portion of data;

writing the aligned portion of data to a first page in a memory device, while coalescing the first unaligned portion of data and a second unaligned portion of data located in a buffer on a controller, wherein a logical page associated with the first unaligned portion of data matches an indicator in a coalescing tree of a logical page associated with the second unaligned portion of data; and

writing the first unaligned portion of data and the second unaligned portion of data to a second page in the memory device.

8. The method of claim 7, wherein the first unaligned portion of data and the second unaligned portion of data are associated with logical addresses that correspond to a particular logical page.

9. The method of claim 8, wherein the method includes creating the indicator corresponding to the second unaligned portion of data that indicates the second unaligned portion of data is associated with the particular logical page.

10. The method of claim 9, wherein the method further includes coalescing the first unaligned portion of data and the second unaligned portion of data responsive to comparing the logical address of the first unaligned portion of data to the indicator.

11. The method of claim 7, wherein the method includes storing the first unaligned portion of data and the second unaligned portion of data in the buffer for coalescing.

12. The method of claim 7, further including:

receiving another write command associated with a third unaligned portion of data and a fourth unaligned portion of data; and

storing the third unaligned portion of data and the fourth unaligned portion of data in the buffer.

13. The method of claim 12, further including coalescing the third unaligned portion of data and a fourth unaligned portion of data responsive to a logical address of the third unaligned portion of data and a logical address of fourth unaligned portion of data being associated with a particular logical page.

14. An apparatus, comprising:

an array of memory cells; and

a controller coupled to the array and configured to;

receive a write command associated with a first unaligned portion of data; and

coalesce, using a coalescing tree, the first unaligned portion of data and a second unaligned portion of data located in a buffer on a controller, wherein the first unaligned portion of data and the second unaligned portion of data are associated with a particular logical page.

15. The apparatus of claim 14, wherein the controller is configured to write the first unaligned portion of data and the second unaligned portion of data to the array in a single write operation.

16. The apparatus of claim 14, wherein the controller is configured to coalesce the first unaligned portion of data and the second unaligned portion of data responsive to the logical addresses associated with the first unaligned portion of data and the second unaligned portion of data corresponding to the particular logical page and the logical addresses not being in common.

17. The apparatus of claim 16, wherein the controller is configured to store the logical addresses associated with the first unaligned portion of data in a read coalescing data structure.

18. The apparatus of claim 16, wherein the controller is configured to store the logical addresses associated with the first unaligned portion of data and the second unaligned portion of data in a write coalescing data structure.

19. The apparatus of claim 14, wherein the controller is configured to create an indicator that refers to the particular logical page corresponding to logical addresses associated with the second unaligned portion of data.

20. The apparatus of claim 14, wherein the controller further comprises a buffer configured to store the first unaligned portion of data and the second unaligned portion of data during coalescing.