Methods and apparatus for locking at least a portion of a shared memory resource

• US 10,191,852 B2
• Filed: 09/22/2016
• Issued: 01/29/2019
• Est. Priority Date: 02/29/2016
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Petkov, Vladislav, Zhang, Haining, Sanghi, Karan, Garg, Saurabh
• Primary Examiner(s): Thai, Tuan
• Application Number:
  US15/273,432
• Publication Number:
  US 20170249098A1
• Time in Patent Office: 859 Days
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0637 Permissions
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 8/63 Image based installation; Cloning; Build to order

Abstract

Methods and apparatus for locking at least a portion of a shared memory resource. In one embodiment, an electronic device configured to lock at least a portion of a shared memory is disclosed. The electronic device includes a host processor, at least one peripheral processor and a physical bus interface configured to couple the host processor to the peripheral processor. The electronic device further includes a software framework that is configured to: attempt to lock a portion of the shared memory; verify that the peripheral processor has not locked the shared memory; when the portion of the shared memory is successfully locked via the verification that the peripheral processor has not locked the portion of the shared memory, execute a critical section of the shared memory; and otherwise attempt to lock the at least the portion of the shared memory at a later time.

Claims

1. A method for locking a shared memory, comprising:

attempting to lock at least a portion of the shared memory by a first processor;

verifying whether a second processor has locked the at least the portion of the shared memory;

responsive to determining that the at least the portion of the shared memory is successfully locked based on the verifying whether the second processor has locked the at least the portion of the shared memory, executing a critical section, the critical section comprising one or more computer instructions accessible only to the first processor; and

otherwise, responsive to determining, based on the verifying whether the second processor has locked the at least the portion of the shared memory, that the at least the portion of the shared memory is not successfully locked, attempting to lock the at least the portion of the shared memory at a later time.

2. The method of claim 1, wherein the attempting to lock the at least the portion of the shared memory at the later time further comprises using a retry-later-lock mechanism.

3. The method of claim 2, wherein the retry-later-lock mechanism comprises using a timer-based mechanism.

4. The method of claim 1, wherein the attempting to lock the at least the portion of the shared memory at the later time further comprises using a spin lock mechanism, the spin lock mechanism enabling the first processor to lock the at least the portion of the shared memory as soon as the second processor releases a lock on the shared memory.

5. The method of claim 1, wherein the attempting to lock the at least the portion of the shared memory by the first processor comprises attempting a global locking mechanism for the shared memory.

6. The method of claim 1, wherein the attempting to lock the at least the portion of the shared memory by the first processor comprises attempting a page table entry locking mechanism for the shared memory.

7. An electronic device configured to lock at least a portion of a shared memory, comprising:

a host processor;

a peripheral processor;

a physical bus interface configured to couple the host processor to the peripheral processor; and

a software framework configured to be executed by the host processor and the peripheral processor, the software framework comprising logic configured to;

attempt to lock the at least the portion of the shared memory;

verify whether the peripheral processor has locked the at least the portion of the shared memory;

in response to a determination that the at least the portion of the shared memory is successfully locked via the verification that the peripheral processor has locked the at least the portion of the shared memory, execute a critical section of the shared memory, the critical section comprising one or more computer instructions accessible only to the host processor; and

otherwise, in response to a determination via the verification that the at least the portion of the shared memory is not locked, attempt to lock the at least the portion of the shared memory at a later time.

8. The electronic device of claim 7, wherein the execution of the critical section of the shared memory comprises a change to a paging table entry within the shared memory.

9. The electronic device of claim 7, wherein the verification that the peripheral processor has not locked the at least the portion of the shared memory comprises a read of a semaphore register located within the peripheral processor.

10. The electronic device of claim 9, wherein the software framework is further configured to write to a semaphore register located within the host processor.

11. The electronic device of claim 10, wherein the critical section of the shared memory prevents the peripheral processor from a performance of a read or a write operation of the at least the portion of the shared memory.

12. The electronic device of claim 7, wherein the successful lock of the at least the portion of the shared memory comprises only a portion of the shared memory being locked for read and write operations by the peripheral processor while other portions of the shared memory remain unlocked for the peripheral processor.

13. The electronic device of claim 7, wherein upon completion of the execution of the critical section, the host processor is configured to release the lock on the at least the portion of the shared memory.

14. A first processor apparatus configured to:

attempt to lock at least a portion of a shared memory;

verify whether a second processor apparatus has locked the at least the portion of the shared memory;

execute a critical section responsive to a determination that the at least the portion of the shared memory is successfully locked based on the verification of whether the second processor apparatus has locked the at least the portion of the shared memory, the critical section comprising one or more computer instructions accessible only to the first processor apparatus; and

otherwise, responsive to a determination that the at least the portion of the shared memory is locked, the determination being based on the verification of whether the second processor apparatus has locked the at least the portion of the shared memory, attempt to lock the at least the portion of the shared memory at a later time.

15. The first processor apparatus of claim 14, wherein the verification whether the second processor apparatus has locked the at least the portion of the shared memory comprises a reading of a semaphore flag of the second processor apparatus.

16. The first processor apparatus of claim 14, wherein the successful lock of the at least the portion of the shared memory comprises prevention of both write operations and read operations of a paging table entry of the shared memory.

17. The first processor apparatus of claim 14, wherein the first processor apparatus is further configured to, before the attempt to lock the at least the portion of the shared memory at the later time, (i) enter an idle state, or (ii) perform operations other than the attempt to lock the at least the portion of the shared memory at the later time.

18. The first processor apparatus of claim 14, wherein the first processor apparatus is further configured to, responsive to the determination that the at least the portion of the shared memory is locked, abandon the attempt to lock the at least the portion of the shared memory.

19. The first processor apparatus of claim 14, wherein the execution of the critical section comprises a change to a paging table entry within the shared memory.

20. The first processor apparatus of claim 14, wherein, upon the execution of the critical section, the host processor is configured to release the lock on the at least the portion of the shared memory.