Memory access protection apparatus and methods for memory mapped access between independently operable processors
First Claim
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1. A method for providing access to a shared memory resource, comprising:
- during a boot process of a second processor;
generating, by a first processor, a first window register value associated with the shared memory resource;
transmitting the first window register value from the first processor to a window register of the second processor, the first window register value defining a first extent of address space within the shared memory resource that is directly accessible by the second processor; and
wherein the first extent of address space is mapped to a memory map of the second processor during the boot process.
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Abstract
Methods and apparatus for providing access to a shared memory resource. In one embodiment, a first processor generates a first window register associated with the shared memory resource; and transmits the first window register from the first processor to a second processor, the first window register defining a first extent of address space within the shared memory resource that is directly accessible by the second processor without requiring a performance of arbitration operations by the first processor.
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Citations
17 Claims
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1. A method for providing access to a shared memory resource, comprising:
during a boot process of a second processor; generating, by a first processor, a first window register value associated with the shared memory resource; transmitting the first window register value from the first processor to a window register of the second processor, the first window register value defining a first extent of address space within the shared memory resource that is directly accessible by the second processor; and wherein the first extent of address space is mapped to a memory map of the second processor during the boot process. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A computing device comprising a memory mapped system, the computing device comprising:
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a host processing device comprising a host central processing unit (CPU) and a host memory management unit (MMU); a peripheral processing device comprising a peripheral CPU, a peripheral MMU, peripheral memory and a peripheral direct memory access (DMA) unit; and a host memory accessible by both the host processing device and the peripheral processing device; wherein the host processing device further comprises logic configured to; generate a first window register value associated with the host memory; transmit the first window register value from the host processing device to the peripheral processing device, the first window register value defining a first extent of address space within the host memory that is directly accessible by the peripheral processing device and that prevents write access of the first extent of address space within the host memory by the host processing device. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A peripheral processing device configured to access host memory within a memory mapped system, the peripheral processing device comprising:
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a peripheral central processing unit (CPU), a peripheral memory management unit (MMU), a peripheral memory and a peripheral direct memory access (DMA) unit and further comprising logic configured to; receive a first window register value from a host processing device during a boot process of the peripheral processing device, the first window register value defining a first extent of address space within the host memory resource that is directly accessible by the peripheral processing device and is not write accessible by the host processing device. - View Dependent Claims (15, 16, 17)
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Specification