Neural network based physical synthesis for circuit designs

• US 10,192,016 B2
• Filed: 01/17/2017
• Issued: 01/29/2019
• Est. Priority Date: 01/17/2017
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Ng, Aaron, Das, Sabyasachi, Basu, Prabal
• Primary Examiner(s): Lin, Sun
• Application Number:
  US15/407,875
• Publication Number:
  US 20180203956A1
• Time in Patent Office: 742 Days
• Field of Search: 716101, 716104
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Physical synthesis for a circuit design can include determining, using a processor, features relating to a signal path of the circuit design not meeting a timing requirement, processing the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate an effectiveness of a first physical synthesis optimization, and selectively performing, using the processor, the first physical synthesis optimization for the signal path based upon a result from the first neural network model.

Claims

1. A method of physical synthesis for a circuit design, the method comprising:

determining, using a processor, features relating to a signal path of the circuit design not meeting a timing requirement;

processing the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate an effectiveness of a first physical synthesis optimization; and

selectively performing, using the processor, the first physical synthesis optimization for the signal path based upon a result from the first neural network model.

2. The method of claim 1, further comprising:

processing the features through a second neural network model trained to indicate an effectiveness of a second physical synthesis optimization; and

selectively applying the second physical synthesis optimization to the signal path based upon a result from the second neural network model.

3. The method of claim 1, wherein the first physical synthesis optimization is performed for the signal path in response to determining that the result from the first neural network model exceeds a threshold.

4. The method of claim 1, further comprising:

training the first neural network model based, at least in part, upon an improvement in slack of timing critical signal paths of a plurality of training circuit designs from applying the first physical synthesis optimization.

5. The method of claim 1, wherein the features of the signal path are normalized and provided to the first neural network model as inputs.

6. The method of claim 1, wherein the features of the signal path include a number of load pins of the signal path.

7. The method of claim 1, wherein the features of the signal path include a number of pins of a driver of the signal path.

8. The method of claim 1, wherein the features of the signal path include a type of a circuit element of a driver of the signal path.

9. The method of claim 1, further comprising:

executing a plurality of neural network models prior to applying the first physical synthesis optimization to the signal path, wherein each neural network model of the plurality of neural network models corresponds to a particular physical synthesis optimization; and

selecting the first physical synthesis optimization based upon results of executing the plurality of neural network models.

10. The method of claim 9, wherein an order of application of at least two synthesis optimizations to the signal path is determined from executing the plurality of neural network models.

11. A system for physical synthesis for a circuit design, the system comprising:

a processor configured to initiate executable operations including;

determining features relating to a signal path of the circuit design not meeting a timing requirement;

processing the features through a first neural network model, wherein the first neural network model is trained to indicate an effectiveness of a first physical synthesis optimization; and

selectively performing the first physical synthesis optimization for the signal path based upon a result from the first neural network model.

12. The system of claim 11, wherein the first physical synthesis optimization is performed for the signal path in response to determining that the result from the first neural network model exceeds a threshold.

13. The system of claim 11, wherein the features of the signal path are normalized and provided to the first neural network model as inputs.

14. The system of claim 11, wherein the features of the signal path include a number of load pins of the signal path.

15. The system of claim 11, wherein the features of the signal path include a number of pins of a driver of the signal path.

16. The system of claim 11, wherein the features of the signal path include a type of a circuit element of a driver of the signal path.

17. The system of claim 11, wherein the processor is configured to initiate executable operations further including:

executing a plurality of neural network models prior to applying the first physical synthesis optimization to the signal path, wherein each neural network model of the plurality of neural network models corresponds to a particular physical synthesis optimization; and

selecting the first physical synthesis optimization based upon results of executing the plurality of neural network models.

18. The system of claim 17, wherein an order of application of at least two synthesis optimizations to the signal path is determined from executing the plurality of neural network models.

19. A computer program product comprising a computer readable storage medium having program code stored thereon, the program code executable by a processor to perform operations comprising:

determining, using the processor, features relating to a signal path of a circuit design not meeting a timing requirement;

processing the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate effectiveness of a first physical synthesis optimization; and

selectively performing, using the processor, the first physical synthesis optimization for the signal path based upon a result from the first neural network model.

20. The computer program product of claim 19, wherein the first physical synthesis optimization is performed for the signal path in response to determining that the result from the first neural network model exceeds a threshold.