Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features
First Claim
1. A DRAM device involving data signals grouped into 10 bits, the device comprising:
- a memory core;
input circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer;
circuitry, including one or both of section circuitry and memory circuitry, that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output, wherein the memory device stores and processes the DBI bit on an internal data bus as a regular data bit; and
a data buffering circuit coupled to the memory core, the data buffering circuit including a write buffer comprising a data register positioned between the input circuitry and the DBI logic and storing the data to be written into the memory core on a later cycle, an address register storing addresses corresponding to the stored data signal, and a comparator comparing a read address to the addresses stored in the write buffer,wherein data from the data register is retrieved as an output data signal instead of data from the DBI logic when the comparator determines that the address stored in the address register matches the read address, thereby causing the output data signal to bypass the DBI logic.
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Abstract
Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.
41 Citations
29 Claims
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1. A DRAM device involving data signals grouped into 10 bits, the device comprising:
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a memory core; input circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer; circuitry, including one or both of section circuitry and memory circuitry, that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output, wherein the memory device stores and processes the DBI bit on an internal data bus as a regular data bit; and a data buffering circuit coupled to the memory core, the data buffering circuit including a write buffer comprising a data register positioned between the input circuitry and the DBI logic and storing the data to be written into the memory core on a later cycle, an address register storing addresses corresponding to the stored data signal, and a comparator comparing a read address to the addresses stored in the write buffer, wherein data from the data register is retrieved as an output data signal instead of data from the DBI logic when the comparator determines that the address stored in the address register matches the read address, thereby causing the output data signal to bypass the DBI logic. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A DRAM memory device involving data signals grouped into 10 bits, the device comprising:
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a memory core; circuitry including transistors and registers/latches arranged and connected to; receive a data bus inversion (DBI) bit, associated with a data signal grouped into 10 bits, as input directly, without transmission through DBI logic associated with an input buffer; store the DBI bit into the memory core; read the DBI bit from the memory core; and
provide the DBI bit as output, wherein the memory device stores and processes the DBI bit on an internal data bus as a regular data bit; anda data buffering circuit coupled to the memory core, the data buffering circuit including a write buffer comprising a data register positioned between the input circuitry and the DBI logic and storing the data to be written into the memory core on a later cycle, an address register storing addresses corresponding to the stored data signal, and a comparator comparing a read address to the addresses stored in the write buffer, wherein data from the data register is retrieved as an output data signal instead of data from the DBI logic when the comparator determines that the address stored in the address register matches the read address, thereby causing the output data signal to bypass the DBI logic. - View Dependent Claims (10, 11)
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12. A DRAM memory system involving data signals grouped into 10 bits, comprising:
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one or more sense lines connecting sense circuitry to output circuitry, wherein at least one sense line is data bus inversion (DBI) formatted and includes a DBI bit; circuitry including transistors, registers, latches and/or components arranged and connected to; receive the DBI bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer; store the DBI bit into a memory core, read the DBI bit from the memory core, and provide the DBI bit as output, wherein the at least one sense line is pre-charged high such that half or more of the lines will be transitioned to a final state of high; and a data buffering circuit coupled to the memory core, the data buffering circuit including a write buffer comprising a data register positioned between the input circuitry and the DBI logic and storing the data to be written into the memory core on a later cycle, an address register storing addresses corresponding to the stored data signal, and a comparator comparing a read address to the addresses stored in the write buffer, wherein data from the data register is retrieved as an output data signal instead of data from the DBI logic when the comparator determines that the address stored in the address register matches the read address, thereby causing the output data signal to bypass the DBI logic. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of DRAM memory operation involving data signals grouped into 10 bits, the method comprising:
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receiving a data bus inversion (DBI) bit and data bits as input; outputting the DBI bit and the data bits to section circuitry; storing the data bits in a data register; comparing an address stored in an address register with a read address; when the address stored in the address register does not match the read address; writing the data bits into bit lines of a memory array; reading the data bits from the memory array; and outputting the DBI formatted data bits and the DBI bits, wherein a data format of the data from the data input, throughout storage in the memory array and one or more write coherency registers, to the data output, is DBI format; and when the address stored in the address register matches the read address; writing the data bits from the data register into bit lines of a memory array, thereby bypassing the DBI converter logic. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29)
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Specification