Charge extraction from ferroelectric memory cell using sense capacitors

• US 10,192,606 B2
• Filed: 04/05/2016
• Issued: 01/29/2019
• Est. Priority Date: 04/05/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Vimercati, Daniele
• Primary Examiner(s): Leboeuf, Jerome
• Application Number:
  US15/090,789
• Publication Number:
  US 20170287541A1
• Time in Patent Office: 1,029 Days
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2255 Bit-line or column circuits
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods

Abstract

A ferroelectric capacitor of a memory cell may be in electronic communication with a sense capacitor through a digit line. The digit line may be virtually grounded during memory cell sensing, limiting or avoiding voltage drop across the digit line, and allowing all or substantially all of the stored charge of the ferroelectric capacitor to be extracted and transferred to the sense capacitor. Virtually grounding the digit line may be achieved by activating a switching component (e.g., a p-type field-effect transistor) that is electronic communication with the digit line. The charge of the ferroelectric capacitor may be transferred through the switching component. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.

Claims

1. A method of operating a ferroelectric memory cell, comprising:

selecting the ferroelectric memory cell that is in electronic communication with a digit line;

activating a switching component that is in electronic communication with the digit line to virtually ground the digit line, wherein activating the switching component comprises applying a charging voltage to a capacitor when the switching component and the capacitor are connected in parallel;

virtually grounding the digit line; and

activating a sense amplifier that is in electronic communication with the digit line based at least in part on virtually grounding the digit line.

2. The method of claim 1, wherein activating the sense amplifier further comprises:

activating the sense amplifier while the digit line is virtually grounded.

3. The method of claim 1, wherein virtually grounding the digit line comprises:

activating the switching component that is in electronic communication between the digit line and the sense amplifier.

4. The method of claim 1, further comprising:

applying a voltage to a ferroelectric capacitor of the ferroelectric memory cell;

charging a sense capacitor that is in electronic communication with the digit line based at least in part on applying the voltage to the ferroelectric capacitor while the digit line is virtually grounded; and

comparing a voltage of the sense capacitor to a reference voltage based at least in part on activating the sense amplifier.

5. The method of claim 1, wherein selecting the ferroelectric memory cell occurs while the digit line is virtually grounded.

6. A method of operating a ferroelectric memory cell, comprising:

activating a switching component that is in electronic communication with a digit line to virtually ground the digit line, wherein the ferroelectric memory cell is in electronic communication with the digit line, wherein activating the switching component comprises applying a charging voltage to a capacitor when the switching component and the capacitor are connected in parallel;

charging a sense capacitor that is in electronic communication with the ferroelectric memory cell while the digit line is virtually grounded, wherein the charging is based at least in part on a voltage applied to the ferroelectric memory cell and comprises transferring a stored charge of the ferroelectric memory cell to the sense capacitor through the switching component; and

comparing a voltage of the sense capacitor to a reference voltage.

7. The method of claim 6, further comprising:

selecting the ferroelectric memory cell using a selection component that is in electronic communication with a ferroelectric capacitor, wherein the ferroelectric memory cell comprises the selection component and the ferroelectric capacitor, and wherein the switching component is activated and the voltage is applied to the ferroelectric capacitor based at least in part on selecting the ferroelectric memory cell.

8. The method of claim 6, further comprising:

deactivating the switching component to isolate the digit line from virtual ground.

9. The method of claim 6, wherein the switching component comprises a transistor, and wherein activating the switching component comprises:

electrically isolating a first terminal of the capacitor from the charging voltage; and

electrically isolating a second terminal of the capacitor from virtual ground.

10. The method of claim 9, wherein applying the charging voltage to the capacitor comprises:

applying a positive charging voltage.

11. The method of claim 6, wherein comparing the voltage of the sense capacitor to the reference voltage comprises:

activating a sense amplifier that is in electronic communication with the sense capacitor.

12. The method of claim 11 wherein comparing the voltage of the sense capacitor to the reference voltage comprises:

charging a reference capacitor that is in electronic communication with the sense amplifier; and

comparing the voltage of the sense capacitor to the voltage of the reference capacitor.

13. An electronic memory apparatus, comprising:

a ferroelectric memory cell that comprises a ferroelectric capacitor and a selection component that is in electronic communication with a digit line;

a sense capacitor in electronic communication with the digit line via a switching component, wherein activating the switching component comprises applying a charging voltage to a capacitor when the switching component and the capacitor are connected in parallel; and

a sense amplifier in electronic communication with the sense capacitor.

14. The electronic memory apparatus of claim 13, wherein a capacitance of the sense capacitor is greater than an intrinsic capacitance of the digit line.

15. The electronic memory apparatus of claim 13, further comprising:

a reference capacitor in electronic communication with the sense amplifier.

16. The electronic memory apparatus of claim 15, wherein the reference capacitor and the sense capacitor have a same capacitance.

17. The electronic memory apparatus of claim 13, wherein the switching component comprises a p-type field-effect transistor (FET).

18. An electronic memory apparatus, comprising:

a ferroelectric memory cell that comprises a ferroelectric capacitor and a selection component;

a sense amplifier in electronic communication with the selection component through a digit line; and

a controller in electronic communication with the selection component and the sense amplifier, wherein the controller is operable to;

operate a switching component to virtually ground the digit line, wherein operating the switching component comprises applying a charging voltage to a capacitor when the switching component and the capacitor are connected in parallel; and

activate the sense amplifier based at least in part on virtually grounding the digit line.

19. The electronic memory apparatus of claim 18, wherein the controller is operable to:

activate the sense amplifier while the digit line is virtually grounded.

20. The electronic memory apparatus of claim 18, further comprising:

a sense capacitor in electronic communication with the digit line through the switching component.

21. The electronic memory apparatus of claim 20, further comprising:

a reference capacitor in electronic communication with the sense amplifier.

22. The electronic memory apparatus of claim 21, wherein the controller is operable to:

compare a voltage of the sense capacitor to a voltage of the reference capacitor to read a logic value of the ferroelectric memory cell.

23. The electronic memory apparatus of claim 18, wherein the controller is operable to:

operate the switching component to virtually ground the digit line that is in electronic communication with the ferroelectric memory cell;

activate the selection component to select the ferroelectric memory cell; and

operate the ferroelectric capacitor of the ferroelectric memory cell to charge a sense capacitor based at least in part on selecting the ferroelectric memory cell.