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Systems, methods, and apparatus for memory cells with common source lines

  • US 10,192,622 B2
  • Filed: 10/12/2017
  • Issued: 01/29/2019
  • Est. Priority Date: 12/02/2013
  • Status: Active Grant
First Claim
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1. A method for operating a memory device, comprising:

  • providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, wherein the first and second memory cells are coupled to a common source line;

    providing a second voltage to a second transistor of the first memory cell and a fourth transistor of the second memory cell; and

    providing a third voltage to the first transistor of the first memory cell and the third transistor of the second memory cell.

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