Systems, methods, and apparatus for memory cells with common source lines
First Claim
Patent Images
1. A method for operating a memory device, comprising:
- providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, wherein the first and second memory cells are coupled to a common source line;
providing a second voltage to a second transistor of the first memory cell and a fourth transistor of the second memory cell; and
providing a third voltage to the first transistor of the first memory cell and the third transistor of the second memory cell.
4 Assignments
0 Petitions
Accused Products
Abstract
A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.
-
Citations
20 Claims
-
1. A method for operating a memory device, comprising:
-
providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, wherein the first and second memory cells are coupled to a common source line; providing a second voltage to a second transistor of the first memory cell and a fourth transistor of the second memory cell; and providing a third voltage to the first transistor of the first memory cell and the third transistor of the second memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method of reading a memory device, comprising:
-
selecting a first memory cell of the memory device for a read operation, wherein the first memory cell and a second memory cell are in a same row and different columns, and wherein the first and second memory cells are coupled to a common source line; providing a first voltage to a first transistor of the first memory cell; and providing a second voltage to a second transistor of the first memory cell. - View Dependent Claims (12, 13, 14)
-
-
15. An apparatus, comprising:
-
a first cell including a first control gate and a first select gate; a second cell including a second control gate and a second select gate; wherein, the first and second cells are in a same row but different columns, the first and second cells are coupled to a common source line, the first and second cells share a first select gate line and a first control gate line, the first select gate line, the first control gate lines, and the common source line extend in a same direction. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification