Non-volatile memory array with memory gate line and source line scrambling

• US 10,192,627 B2
• Filed: 04/17/2018
• Issued: 01/29/2019
• Est. Priority Date: 12/08/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Chen, Chun, Betser, Yoram, Chang, Kuo Tung, Givant, Amichai, Shetty, Shivananda, Fang, Shenqing
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US15/954,955
• Publication Number:
  US 20180261295A1
• Time in Patent Office: 287 Days
• Field of Search: 36518517, 36518501
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.

Claims

1. A memory device, comprising:

a plurality of non-volatile memory (NVM) cells, each including a memory gate, arranged in rows and columns, wherein memory gates of first and second NVM cells of a first column are electrically insulated from one another, and wherein memory gates of third and fourth NVM cells of the first column are electrically insulated from one another; and

a first source line coupled to the first and second NVM cells, and a second source line coupled to the third and fourth NVM cells of the first column, wherein the first and second source lines are adjacent and electrically insulated from one another, and wherein each of the first and second source lines respectively shares a common electrical node to receive a same voltage signal with at least one source line of the first column other than the first and second source lines.

2. The memory device of claim 1, wherein a memory array of the memory device is at least partly formed by coupling a plurality of the first, second, third, and fourth NVM cells, wherein a first plurality of the first, second, third, and fourth NVM cells are coupled to form the first column of the memory array, and wherein a pattern of the first column is repeated in at least one remaining columns of the memory array.

3. The memory device of claim 2, wherein configurations of the rows and the columns of the memory array are reversed.

4. The memory device of claim 1, wherein the first and second NVM cells include a mirrored orientation, the first and second memory gates face one another, and the first source line disposed between the first and second memory gates, and wherein the third and fourth NVM cells include the mirrored orientation, the third and fourth memory gates face one another, and the second source line is disposed between the third and fourth memory gates.

5. The memory device of claim 1, wherein the first, second, third, and fourth NVM cells include a split gate memory cell configuration.

6. The memory device of claim 1, wherein the first, second, third, and fourth NVM cells include a two-transistor memory cell configuration, and wherein the two-transistor memory cell includes one field-effect-transistor, and one silicon-oxide-nitride-oxide-silicon transistor or one floating gate transistor.

7. The memory device of claim 1, wherein when the first memory cell is selected for a program operation and the second memory cell is not selected for the program operation, the first and second memory gates are configured to receive a high voltage and a low voltage, respectively from two different memory gate driver circuits.

8. The memory device of claim 1, wherein when the second memory cell is selected for a program operation and the third memory cell is not selected for the program operation, the second and third memory gates are configured to receive a high voltage, wherein the first and second source lines are configured to receive a high source voltage and a low source voltage, respectively from two different source line driver circuits.

9. The memory device of claim 8, wherein the high voltage is in an approximate range of 5 V to 10 V, and the low voltage in an approximate range of 0 V to 5 V.

10. A memory array, comprising:

non-volatile memory (NVM) cells, each including a memory gate and a select gate, arranged in rows and columns, wherein,

two adjacent NVM cells of a same column that share a source region form an NVM pair, wherein the source region is disposed between memory gates of the two adjacent NVM cells, and wherein multiple NVM pairs are coupled to one another in the same column,

at least two memory gates of NVM cells of a same row share a memory gate line,

at least two source regions of NVM cells of the same row share a source line; and

source line connection routing configured to provide multiple common electrical nodes, wherein each of the multiple common electrical node is shared among multiple source lines of a same source line group to receive a same voltage signal, and wherein the multiple source lines in the same source line group are not physically adjacent to one another.

11. The memory array of claim 10, wherein:

at least two select gates of NVM cells of the same row share a select gate line; and

at least two drain regions of NVM cells of the same column share a bit line, wherein the drain region of each of the NVM cells is disposed adjacent to the select gate.

12. The memory array of claim 10, wherein each of the source line groups is coupled with a separate source line driver circuit, configured to receive a separate source voltage.

13. The memory array of claim 10, further comprising:

memory gate connection routing configured to connect multiple memory gate lines electrically to form multiple memory gate line groups, wherein the multiple memory gate lines in a same memory gate line group do not share any source line that is in a same source line group, and wherein each of the multiple memory gate line groups is coupled with a separate memory gate line driver circuit, configured to receive a separate memory gate voltage.

14. The memory array of claim 13, wherein the NVM cells in the multiple source lines in a same source line group do not include memory gate lines that are in the same memory gate line group.

15. The memory array of claim 10 comprising 2N rows of NVM cells, N being a natural number, wherein:

multiple odd source lines including 1^st to (N−

1)^th source lines are connected electrically by a first source line connection routing;

multiple even source lines including 0^th to (N−

2)^th source lines are connected electrically by a second source line connection routing; and

the first and second source line connection routings are coupled to two different source line driver circuits.

16. The memory array of claim 10 comprising 2N rows of NVM cells, N being a natural number, wherein:

0^th and (2N−

1)^th memory gate lines are connected electrically by a first memory gate line connection routing;

at least one remaining odd memory gate line is connected electrically to its adjacent even memory gate line by a second memory gate line connection routing; and

the first and the second memory gate line connection routing are each coupled to a separate memory gate driver circuit.

17. The memory array of claim 13, wherein the memory gate connection routing includes metal 1 (M1) connection to the memory gate driver circuit.

18. The memory array of claim 10, wherein the NVM cells include two-transistor memory cells.

19. The memory array of claim 10, wherein the NVM cells include split gate memory cells.

20. A method, comprising:

providing a non-volatile memory (NVM) array, wherein the non-volatile memory array includes at least four non-volatile memory (NVM) cells coupled in a same column of the NVM array, wherein each NVM cell includes a memory gate and a select gate, wherein first and second NVM cells of the at least four NVM cells share a first source line, and third and fourth NVM cells share a second source line, and wherein the first and second source lines each shares a common electrical node with at least another source line of the same column to receive a same voltage signal that is not adjacent to the first and second source lines respectively;

coupling a high select voltage to a first select gate to select the first memory cell for a program operation;

coupling a low select voltage to a second select gate to unselect the second memory cell for the program operation;

coupling a high program voltage to the first memory gate and a low inhibit voltage to the second memory gate; and

coupling two different source voltages to the first source line and the second source line from two different source line driver circuits, respectively.

21. The method of claim 20, wherein the memory gates of the second and third NVM cells are electrically connected, and wherein the first and second source lines are physically adjacent to one another.