Methods of fabricating dual threshold voltage devices with stacked gates

• US 10,192,788 B1
• Filed: 01/08/2018
• Issued: 01/29/2019
• Est. Priority Date: 01/08/2018
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Transfer Technologies
• Inventors: Sharma, Gian, Levi, Amitay, Kim, Kuk-Hwan
• Primary Examiner(s): Payen, Marvin
• Assistant Examiner(s): Joy, Jeremy
• Application Number:
  US15/865,132
• Time in Patent Office: 386 Days
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/5607 using magnetic storage elements
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/80 : Constructional details
• CPC Class Codes: H10N 50/85 : Magnetic active materials

Abstract

A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Claims

1. A method of fabricating a cylindrical device with aligned input terminals, comprising:

providing a conductive core corresponding to a first transistor, and forming a plurality of cylindrical layers around the conductive core, including a first dielectric layer, a second layer, a third dielectric layer, and a fourth conductive layer corresponding to a second transistor;

forming a first input terminal coupled with the first transistor; and

forming a second input terminal coupled with the second transistor, wherein;

the first input terminal and the second input terminal extend radially outward from the cylindrical device, and

the first input terminal is vertically aligned with the second input terminal.

2. The method of claim 1, further comprising creating a silicide source, including:

depositing multiple layers in succession on an oxidized silicon substrate, the multiple layers including at least an oxide layer and a planarization layer;

removing, at least partially, the oxide layer and the planarization layer until the oxide substrate is exposed;

removing, at least partially, the oxide layer to expose a horizontal cross section of the cylindrical device to create an annular area; and

after the removing, depositing a siliciding metal on the annular area to form the silicide source.

3. The method of claim 2, wherein the silicide source is coupled with the first and second transistors.

4. The method of claim 2, wherein the annular area is at a bottom of the cylindrical device.

5. The method of claim 2, further comprising applying a mask after depositing the multiple layers and before the removing, wherein the mask protects the cylindrical core and one or more layers of the plurality of cylindrical layers during the removing.

6. The method of claim 2, wherein:

the oxide layer is a first oxide layer; and

the method further comprises creating the second input terminal, including;

depositing a second oxide layer to create an oxide plane;

depositing a spin-on glass (SOG) layer on the oxide plane, wherein the cylindrical device is vertically disposed in the oxide plane;

depositing an organic compound to create an organic planarization layer (OPL), wherein the OPL surrounds a horizontal cross section of the cylindrical device;

depositing a third oxide layer onto the OPL, wherein the third oxide layer surrounds a horizontal cross section of the cylindrical device;

removing portions of the OPL and the third oxide layer until a portion of the SOG layer is exposed, thereby forming a trench; and

depositing, to a first height, a metal compound in the trench partially filling the trench to leave space for the first input terminal to also be formed in the trench, wherein the metal compound forms the second input terminal.

7. The method of claim 6, further comprising etching the SOG layer to a first thickness before depositing the organic compound.

8. The method of claim 6, wherein the removing involves is a fluorine-based chemistry and/or oxygen plasma.

9. The method of claim 6, further comprising depositing an anti-reflective coating on the third oxide layer before the removing.

10. The method of claim 6, further comprising depositing a photoresist layer on the anti-reflective coating, wherein the anti-reflective coating and the photoresist layer surround a horizontal cross section of the cylindrical device.

11. The method of claim 10, further comprising creating a mask with the photoresist layer before removing the anti-reflective coating and the second oxide layer using the fluorine-based chemistry, wherein a shape of the trench is defined by the mask.

12. The method of claim 6, further comprising creating the first input terminal, including:

depositing, on top of the second input terminal formed in the partially full trench, a first dielectric layer to a second height to create a first dielectric plane, wherein first dielectric layer does not fill the trench to leave space for the first input terminal to also be formed in the trench;

etching through the plurality of cylindrical layers in parallel with the trench, wherein;

the etching stops at the second height such that the first dielectric layer defines a lower boundary of the trench, and

the etching extends the partially full trench through the plurality of cylindrical layers to the cylindrical core;

depositing a second dielectric layer substantially filling the trench to create a second dielectric plane, wherein an upper boundary of the second dielectric layer substantially parallels a top of the cylindrical device; and

depositing a metal gate contact on the second dielectric plane, wherein the metal gate contact contacts the conductive core, and the second dielectric layer in combination with metal gate contact form the first input terminal.

13. The method of claim 12, wherein the metal gate contact material is tantalum nitride.

14. The method of claim 12, wherein the first and second dielectric layers are silicon nitride (SiN).

15. The method of claim 1, wherein the two transistors have dual threshold voltages.

16. The method of claim 1, wherein forming the plurality of cylindrical layers around the cylindrical core comprises:

depositing a spin-on glass (SOG) layer on a first plane of the cylindrical device to create a sloped ring around the bottom of the cylindrical device, wherein the cylindrical device is vertically disposed in the first plane and the SOG layer surrounds the cylindrical device;

etching the SOG layer from around and inside the cylindrical device to a desired depth;

depositing one or more dielectric materials to form the third dielectric layer;

depositing a doped material on the first plane, a horizontal cross section of the cylindrical device, a top of the cylindrical device, and the sloped ring;

etching the doped material on the top of the cylindrical device and on the sloped ring; and

depositing a siliciding metal to create the fourth conductive layer.

17. The method of claim 16, further comprising performing a third RTA to finish creation of the fourth conductive layer.

18. The method of claim 16, further comprising wet etching the siliciding metal after the third RTA.