Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound

• US 10,192,801 B2
• Filed: 03/20/2012
• Issued: 01/29/2019
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Lin, Yaojian, Fang, Jianmin, Chen, Kang, Cao, Haijing
• Primary Examiner(s): Graybill, David E
• Application Number:
  US13/424,484
• Publication Number:
  US 20120175784A1
• Time in Patent Office: 2,506 Days
• Field of Search: None
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a first semiconductor die disposed over a first surface of the semiconductor substrate;

a capacitor formed over the first surface of the semiconductor substrate and laterally offset from the first semiconductor die, the capacitor including,

(a) a first conductive layer formed over the first surface of the semiconductor substrate,

(b) an insulating layer formed over the first conductive layer, and

(c) a second conductive layer formed over the insulating layer;

an encapsulant deposited around the first semiconductor die and over the capacitor;

a vertical interconnect structure formed through the encapsulant; and

a third conductive layer formed over a surface of the encapsulant opposite the capacitor, wherein the third conductive layer is in physical contact with the vertical interconnect structure and a portion of the third conductive layer is wound to form an inductor.

2. The semiconductor device of claim 1, further including a resistor formed over the first conductive layer.

3. The semiconductor device of claim 1, wherein a thickness of the encapsulant over the capacitor is at least 50 micrometers.

4. The semiconductor device of claim 1, further including a second semiconductor die disposed over a second surface of the semiconductor substrate opposite the first surface of the semiconductor substrate.

5. The semiconductor device of claim 1, further including a heat sink disposed over the first semiconductor die.

6. The semiconductor device of claim 1, further including a second semiconductor die disposed over the first semiconductor die.

24. The semiconductor device of claim 1, further including a plurality of conductive vias formed through the semiconductor substrate.

7. A semiconductor device, comprising:

a semiconductor substrate;

a conductive via formed through the semiconductor substrate;

a first semiconductor die disposed over a first surface of the semiconductor substrate;

a first integrated passive device (IPD) formed over the first surface of the semiconductor substrate and laterally offset from the first semiconductor die;

an encapsulant deposited in contact with the first semiconductor die and first IPD; and

a second IPD formed over a surface of the encapsulant opposite the first IPD and laterally offset from the first semiconductor die, wherein the second IPD includes a first conductive layer formed over the surface of the encapsulant and wound to form an inductor.

8. The semiconductor device of claim 7, wherein the first IPD includes a capacitor or resistor.

9. The semiconductor device of claim 7, further including a heat sink disposed over the first semiconductor die.

10. The semiconductor device of claim 7, further including an interconnect structure formed through the encapsulant, wherein the first conductive layer formed over the surface of the encapsulant contacts the interconnect structure.

11. The semiconductor device of claim 7, further including a second semiconductor die disposed over the first semiconductor die.

23. The semiconductor device of claim 7, wherein the first IPD includes:

a second conductive layer formed over the first surface of the semiconductor substrate;

an insulating layer formed over the second conductive layer; and

a third conductive layer formed over the insulating layer.

25. The semiconductor device of claim 7, further including a second semiconductor die disposed over a second surface of the semiconductor substrate opposite the first surface of the semiconductor substrate.

12. A semiconductor device, comprising:

a substrate including a semiconductor material;

a first semiconductor die disposed over a first surface of the substrate;

a first integrated passive device (IPD) disposed over the first surface of the substrate and laterally offset from the first semiconductor die;

an encapsulant deposited over the first IPD; and

a second IPD formed over a surface of the encapsulant opposite the first IPD and laterally offset from the first semiconductor die, wherein the second IPD includes a first conductive layer formed over the surface of the encapsulant opposite the first IPD and wound to form an inductor.

13. The semiconductor device of claim 12, further including a conductive via formed through the substrate.

14. The semiconductor device of claim 12, further including a second semiconductor die disposed over the first semiconductor die.

15. The semiconductor device of claim 12, wherein the first IPD includes a capacitor or resistor.

16. The semiconductor device of claim 12, wherein the first IPD includes:

a second conductive layer;

an insulating layer formed over the second conductive layer; and

a third conductive layer formed over the insulating layer.

17. The semiconductor device of claim 12, further including an interconnect structure formed through the encapsulant, wherein the first conductive layer contacts the interconnect structure.

26. The semiconductor device of claim 12, further including a second conductive layer formed over the second IPD.

18. A semiconductor device, comprising:

a substrate including a semiconductor material;

a first semiconductor die disposed over a surface of the substrate;

an integrated passive device (IPD) disposed over the surface of the substrate laterally offset from the first semiconductor die;

an encapsulant deposited over the IPD;

an interconnect structure formed through the encapsulant; and

a first conductive layer wound to form an inductor over a surface of the encapsulant opposite the IPD and in contact with the interconnect structure.

19. The semiconductor device of claim 18, further including a second semiconductor die disposed over the first semiconductor die.

20. The semiconductor device of claim 18, wherein the IPD includes a capacitor or resistor.

21. The semiconductor device of claim 18, wherein the IPD includes:

a second conductive layer formed over the surface of the substrate;

an insulating layer formed over the second conductive layer; and

a third conductive layer formed over the insulating layer.

22. The semiconductor device of claim 18, further including an insulating layer formed over the encapsulant, wherein the first conductive layer is formed over the insulating layer.