Array substrate and manufacturing method thereof, display device

• US 10,192,904 B2
• Filed: 07/25/2014
• Issued: 01/29/2019
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Liu, Xiang
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US14/432,048
• Publication Number:
  US 20160027820A1
• Time in Patent Office: 1,649 Days
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/469 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques encapsulating layers H01L21/56; After-treatment of these layers
• CPC Class Codes: H01L 21/47573 Etching the layer
• CPC Class Codes: H01L 21/47635 After-treatment of these layers
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/24 : including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/4908 : for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 : of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A manufacturing method of an array substrate, including: forming a pattern layer including a pixel electrode, and a pattern layer including a gate electrode and a gate line on a base substrate; on the substrate with the pattern layer including the gate electrode and the gate line formed thereon, forming a gate insulating layer, a pattern layer at least including a metal oxide semiconductor active layer and a pattern layer at least including an etch stop layer; wherein, a first via hole for exposing the pixel electrode is formed over the pixel electrode; on the substrate with the etch stop layer formed thereon, forming a pattern layer including a source electrode, a drain electrode and a data line; wherein, the source electrode and the drain electrode each contact a metal oxide semiconductor active layer, and the drain electrode is electrically connected to the pixel electrode through the first via hole.

Claims

1. A manufacturing method of an array substrate, comprising:

forming, on a base substrate and via one patterning process, a transparent conductive pattern layer, a pattern layer including a pixel electrode, and a pattern layer including a gate electrode and a gate line, the transparent conductive pattern lying in a same level as the pixel electrode;

on the substrate with the pattern layer including the gate electrode and the gate line formed thereon, through one patterning process or two patterning processes, forming a gate insulating layer, a pattern layer at least including a metal oxide semiconductor active layer and a pattern layer at least including an etch stop layer, wherein the etch stop layer comprises a first portion which is, along a gate line direction, between a second via hole and a third via hole that are located on two sided of the gate electrode;

wherein, a first via hole for exposing the pixel electrode is formed over the pixel electrode; and

on the substrate with the etch stop layer formed thereon, through one patterning process, forming a pattern layer including a source electrode, a drain electrode and a data line, wherein, the source electrode and the drain electrode each contact with the metal oxide semiconductor active layer, and the drain electrode and the pixel electrode are electrically connected through the first via hole.

2. The manufacturing method according to claim 1, wherein, on the substrate with the pattern layer including the gate electrode and the gate line formed thereon, through one patterning process or two patterning processes, forming the gate insulating layer, the pattern layer at least including the metal oxide semiconductor active layer and the pattern layer at least including the etch stop layer includes:

on the substrate with the pattern layer including the gate electrode and the gate line formed thereon, forming a gate insulating layer thin film, a metal oxide semiconductor active layer thin film and an etch stop layer thin film in sequence, and forming photoresist on the etch stop layer thin film;

conducting an exposure of the substrate with the photoresist formed thereon by using a second gray-tone mask or a second half-tone mask, so as to form a photoresist fully-retained portion, a photoresist half-retained portion and a photoresist fully-removed portion after development;

wherein, the photoresist half-retained portion corresponds to regions where a second via hole for connecting the source electrode and the metal oxide semiconductor active layer, and a third via hole for connecting the drain electrode and the metal oxide semiconductor active layer are to be formed;

the photoresist fully-removed portion corresponds to the first via hole for connecting the drain electrode and the pixel electrode, and a fourth via hole and a fifth via hole, which are to be formed so that the fourth via hole and the fifth via hole are located between the first via hole and the second via hole that are located between two adjacent gate electrodes, the fourth via hole is close to the first via hole, and the fifth via hole is close to the second via hole; and

the photoresist fully-retained portion corresponds to the other region;

removing the etch stop layer thin film, the metal oxide semiconductor active layer thin film and the gate insulating layer thin film of the photoresist fully-removed portion by using an etch process, so as to form the gate insulating layer with the first via hole, the fourth via hole and the fifth via hole, and to form a pattern layer including the metal oxide semiconductor active layer with the first via hole and a metal oxide semiconductor active layer retained pattern;

wherein, the metal oxide semiconductor active layer retained pattern is confined by a region between the fourth via hole and the fifth via hole that are located between any two of the gate electrodes that are adjacent;

removing the photoresist of the photoresist half-retained portion by using an ashing process;

removing exposed etch stop layer thin film by using etch process, so as to form the second via hole and the third via hole, as well as a pattern layer including the first portion of the etch stop layer and a second portion of the etch stop layer which is an etch stop layer retained pattern;

wherein, other remaining etch stop layer thin film is the etch stop layer retained pattern; and

removing the photoresist of the photoresist fully-retained portion by using a stripping process.

3. The manufacturing method according to claim 2, wherein, the first via hole and the third via hole have a spacing therebetween.

4. The manufacturing method according to claim 2, wherein, the first via hole is joined to the third via hole.

5. The manufacturing method according to claim 1, wherein, forming the transparent conductive pattern layer, the pattern layer including the pixel electrode, and the pattern layer including the gate electrode and the gate line includes:

sequentially forming a transparent conductive thin film and a metal thin film on the base substrate, and forming photoresist on the metal thin film;

conducting an exposure of the substrate with the photoresist formed thereon by using a third gray-tone mask or a third half-tone mask, so as to form a photoresist fully-retained portion, a photoresist half-retained portion and a photoresist fully-removed portion after development;

wherein, the photoresist fully-retained portion corresponds to a region where the pattern layer including the gate electrode and the gate line is to be formed, the photoresist half-retained portion corresponds to a region where the pattern layer including the pixel electrode is to be formed, and the photoresist fully-removed portion corresponds to the other region;

removing the metal thin film and the transparent conductive thin film of the photoresist fully-removed portion by using an etch process, so as to form the pattern layer including the gate electrode and the gate line as well as a transparent conductive pattern layer under the pattern layer including the gate electrode and the gate line, the pixel electrode, and a part of metal thin film over the pixel electrode;

removing the photoresist of the photoresist half-retained portion by using an ashing process;

removing the part of the metal thin film over the pixel electrode that has been exposed by using etch process; and

removing the photoresist of the photoresist fully-retained portion by using stripping process.

6. The manufacturing method according to claim 1, further comprising, forming a passivation layer and a common electrode on the substrate with the source electrode, the drain electrode and the data line formed thereon.

7. An array substrate, comprising:

a pattern layer including a gate electrode and a gate line;

a gate insulating layer;

a metal oxide semiconductor active layer;

a pixel electrode; and

a pattern layer including a source electrode, a drain electrode and a data line;

wherein, the array substrate further includes;

a transparent conductive pattern layer disposed under the pattern layer including the gate electrode and the gate line, the transparent conductive pattern lying in a same level as the pixel electrode; and

an etch stop layer disposed over the metal oxide semiconductor active layer, wherein, the source electrode and the drain electrode are located over the etch stop layer, and the drain electrode is electrically connected to the pixel electrode through a first via hole located over the pixel electrode,

wherein the etch stop layer comprises a first portion which is, along a gate line direction, between a second via hole and a third via hole that are located on two sides of the gate electrode.

8. The array substrate according to claim 7, further comprising:

a metal oxide semiconductor active layer retained pattern in the same layer as the metal oxide semiconductor active layer; and

a second portion of the etch stop layer, which is an etch stop layer retained pattern in the same layer as the first portion of the etch stop layer;

wherein,

the metal oxide semiconductor active layer retained pattern is confined by a region between a fourth via hole located between any two of the gate electrodes that are adjacent and close to the first via hole, and a fifth via hole located on the right side of the fourth via hole and close to the second via hole; and

the source electrode contacts the metal oxide semiconductor active layer through the second via hole, the drain electrode contacts the metal oxide semiconductor active layer through the third via hole, and the drain electrode is electrically connected to the pixel electrode through the first via hole.

9. The array substrate according to claim 8, wherein, the first via hole and the third via hole have a spacing therebetween.

10. The array substrate according to claim 8, wherein, the first via hole is joined to the third via hole.

11. The array substrate according to claim 7, wherein, the array substrate further includes a passivation layer and a common electrode.

12. A display device, comprising the array substrate according to claim 7.

13. The array substrate according to claim 9, wherein, the first via hole is joined to the third via hole.

14. The array substrate according to claim 8, wherein, the array substrate further includes a passivation layer and a common electrode.

15. The display device according to claim 12, further comprising:

a metal oxide semiconductor active layer retained pattern in the same layer as the metal oxide semiconductor active layer; and

a second portion of the etch stop layer, which is an etch stop layer retained pattern in the same layer as the first portion of the etch stop layer;

wherein,

the metal oxide semiconductor active layer retained pattern is confined by a region between a fourth via hole located between any two of the gate electrodes that are adjacent and close to the first via hole, and a fifth via hole located on the right side of the fourth via hole and close to the second via hole; and

the source electrode contacts the metal oxide semiconductor active layer through the second via hole, the drain electrode contacts the metal oxide semiconductor active layer through the third via hole, and the drain electrode is electrically connected to the pixel electrode through the first via hole.

16. The display device according to claim 15, wherein, the first via hole and the third via hole have a spacing therebetween.

17. The display device according to claim 15, wherein, the first via hole is joined to the third via hole.

18. The display device according to claim 12, wherein, the array substrate further includes a passivation layer and a common electrode.