Image sensor including dual isolation and method of making the same

• US 10,192,918 B2
• Filed: 10/19/2015
• Issued: 01/29/2019
• Est. Priority Date: 04/03/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jeng-Shyan, Yaung, Dun-Nian, Liu, Jen-Cheng, Chuang, Chun-Chieh, Chien, Volume
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): Chi, Suberr
• Application Number:
  US14/886,290
• Publication Number:
  US 20160043121A1
• Time in Patent Office: 1,198 Days
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

An image sensor includes a substrate having a pixel region and a periphery region. The image sensor further includes a first isolation structure formed in the pixel region; the first isolation structure including a first trench having a first depth. The image sensor further includes a second isolation structure formed in the periphery region; the second isolation structure including a second trench having a second depth. The second depth is greater than the first depth.

Claims

1. A method comprising:

providing a mask over a substrate, wherein the substrate has a pixel area and a periphery area;

patterning a first opening in the pixel area and a second opening in the periphery area;

etching the mask via the first opening and the second opening;

protecting an entirety of the periphery area;

etching the substrate via the first opening to form a first STI structure having a first depth;

protecting the pixel area;

etching the substrate via the second opening to form a second STI structure having a second depth deeper than the first depth;

depositing an oxide layer in the first and the second STI structures;

removing the mask and an entirety of the oxide layer located above a top surface of the substrate, wherein after removal a surface of the oxide layer is coplanar with the top surface of the substrate;

forming at least one photo detector comprising one or more first NMOS devices in the pixel area, with the proviso that the pixel area does not contain any PMOS devices; and

forming second NMOS devices and PMOS devices in the periphery area.

2. The method of claim 1, wherein the depositing of the oxide layer comprises using a high density plasma (HDP) or a tetraethyl orthosilicate (TEOS) technique.

3. The method of claim 1, wherein the mask is selected from the group consisting of SiN film and SiON.

4. The method of claim 1, wherein the substrate is a semiconductor device selected from the group consisting of a CMOS image sensor, an active pixel sensor, a charge coupled device sensor, and an embedded DRAM.

5. The method of claim 1, wherein the substrate is a CMOS image sensor selected from front-side illumination and backside illumination.

6. The method of claim 1, wherein the first depth ranges from 100 Å

to 4000 Å and

the second depth ranges from 2500 Å

to 4500 Å

.

7. The method of claim 1, further comprising depositing an oxide layer between the substrate and the mask and etching the oxide layer via the first opening and the second opening.

8. The method of claim 1, wherein removing the mask and the entirety of the oxide layer located above the top surface of the substrate comprises using chemical mechanical polishing.

9. A method comprising:

patterning a first photo resist layer over a mask to expose a first portion of a substrate, wherein the first portion is in a pixel array region of the substrate;

etching the mask and the first portion of the substrate using the first photo resist layer as a lithography mask to form a first opening having a first depth in the first portion of the substrate;

protecting the first portion of the substrate using a second photo resist layer, wherein the second photo resist layer exposes a second portion of the substrate, the second portion is in a peripheral region of the substrate, the second portion is protected during the etching of the first portion;

etching the mask and the second portion of the substrate to form a second opening having a second depth in the second portion of the substrate, wherein the second depth is greater than the first depth;

filling the first opening and the second opening with an insulating material;

forming at least one photo detector in the pixel array region, wherein the forming of the at least one photo detector comprises forming one or more first NMOS devices in the pixel array region with the proviso that the pixel array region does not contain any PMOS devices; and

forming second NMOS devices and PMOS devices in the peripheral region.

10. The method of claim 9, wherein etching the second portion comprises etching the second portion after protecting the first portion.

11. The method of claim 9, wherein etching the first portion occurs prior to protecting the first portion.

12. A method comprising:

providing a mask over a substrate, wherein the substrate has a pixel area and a periphery area;

depositing a photo resist layer over the mask;

patterning the photo resist layer to form an opening therein;

etching the mask and the substrate via the opening using the photo resist layer as a lithography mask to form a first STI structure having a first depth in the pixel area, wherein the periphery area is protected during the etching of the mask and the substrate;

protecting the pixel area;

etching the mask and the substrate to form a second STI structure in the periphery area, the second STI structure having a second depth deeper than the first depth;

forming at least one photo detector comprising one or more first NMOS devices in the pixel area, with the proviso that the pixel area does not contain any PMOS devices; and

forming second NMOS devices and PMOS devices in the periphery area.

13. The method of claim 12, further comprising depositing a first oxide layer in the first and the second STI structures.

14. The method of claim 13, wherein the depositing of the first oxide layer comprises using a high density plasma (HDP) or a tetraethyl orthosilicate (TEOS) technique.

15. The method of claim 13, further comprising depositing a second oxide layer between the substrate and the mask.

16. The method of claim 15, further comprising etching the second oxide layer to form the first STI and the second STI structure.

17. The method of claim 16, further comprising:

depositing another photo resist layer to cover the first STI structure and the mask; and

patterning the another photo resist layer to form another opening therein,

wherein the forming of the second STI structure comprises etching the mask, the second oxide layer and the substrate via the another opening.

18. The method of claim 17, further comprising removing the mask and the second oxide layer from the substrate.

19. The method of claim 12, wherein the providing of the mask comprises depositing the mask over both the pixel area and the periphery area.

20. The method of claim 12, wherein the providing of the mask over the substrate comprises depositing a SiN film or a SiON film over the substrate.