Inductor element, inductor element manufacturing method, and semiconductor device with inductor element mounted thereon

• US 10,192,951 B2
• Filed: 02/05/2018
• Issued: 01/29/2019
• Est. Priority Date: 08/01/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Hijioka, Kenichiro, Tanabe, Akira, Hayashi, Yoshihiro
• Primary Examiner(s): Chan, Tsz
• Application Number:
  US15/888,594
• Publication Number:
  US 20180175136A1
• Time in Patent Office: 358 Days
• Field of Search: 336200, 336232
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/002 Details of via holes for interconnecting the layers
• CPC Class Codes: H01F 2017/004 with the coil helically wound around an axis without a core
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate inductors for integrated circuits H01L28/10
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49071 by winding or coiling

Abstract

An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a multiple layer lead structure formed over the semiconductor substrate; and

a coil formed in the multiple layer lead structure,

wherein the coil comprises;

a first coiled lead formed in a first layer;

a second coiled lead formed in a second layer;

a third coiled lead formed in the first layer;

a first via connected to the first coiled lead and the second coiled lead; and

a second via connected to the second coiled lead and the third coiled lead,

wherein each of the first coiled lead and the third coiled lead have one complete wind,

wherein the second coiled lead has two winds,

wherein the third coiled lead encircles the first coiled lead,

wherein an inter-lead capacitance of the first coiled lead and the second coiled lead is larger than an inter-lead capacitance between the first coiled lead and the third coiled lead,

wherein at least one of the first, second, and third coiled leads includes a plurality of slits which are discontinuous in a longitudinal direction of the at least one of the first, second, and third coiled leads, and the plurality of slits are formed in parallel at a plurality of corners and the plurality of slits run parallel along entire liner portions of the at least one of the first, second, and third coiled leads.

2. The semiconductor device according to claim 1, wherein a distance between the first coiled lead and the third coiled lead is longer than a distance between the second coiled lead and the third coiled lead.

3. The semiconductor device according to claim 1, wherein the first coiled lead and the third coiled lead are positioned above the second coiled lead.

4. The semiconductor device according to claim 1, wherein the first coiled lead and an inner side of the second coiled lead overlap in a planar view.

5. The semiconductor device according to claim 1, wherein an outer side of the second coiled lead and the third coiled lead overlap in a planar view.

6. The semiconductor device according to claim 1, wherein the first coiled lead and the third coiled lead do not overlap in a planar view.

7. The semiconductor device according to claim 1, wherein the first via and the second via are on a same layer.

8. The semiconductor device according to claim 1, wherein, a winding direction of the coil is unidirectional.

9. The semiconductor device according to claim 1, wherein at least one of the first, second, and third coiled leads includes at least two rows of slits, each of the at least two rows of slits comprising the plurality of slits aligned in a length-wise direction of the at least one of the first, second and third coiled leads.

10. The semiconductor device according to claim 1, wherein the plurality of slits comprise at least one slit having a C-shape that is open at a longitudinal direction end of the at least one of the first, second and third coiled leads;

at least one slit having a rectangular shaped aperture in a straight line portion of the at least one of the first, second and third coiled leads; and

at least one slit having a bent rectangular shaped aperture at a bent portion of the at least one of the first, second and third coiled leads.