Semiconductor device and method of manufacturing the same
First Claim
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1. A method of manufacturing a semiconductor device, comprising:
- forming a crystalline oxide semiconductor layer;
forming a first insulating layer over the crystalline oxide semiconductor layer;
forming a gate electrode over the crystalline oxide semiconductor layer with the first insulating layer positioned therebetween;
forming a gate insulating layer by etching the first insulating layer with the gate electrode used as a mask until the crystalline oxide semiconductor layer is partly exposed; and
forming a crystalline region containing nitrogen in the crystalline oxide semiconductor layer by performing nitrogen plasma treatment on the exposed part of the crystalline oxide semiconductor layer,wherein the crystalline oxide semiconductor layer is a c-axis aligned crystalline oxide semiconductor layer, andwherein after the step of forming the gate insulating layer edges of the gate electrode and edges of the gate insulating layer are aligned.
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Abstract
A transistor which includes an oxide semiconductor and is capable of high-speed operation and a method of manufacturing the transistor. In addition, a highly reliable semiconductor device including the transistor and a method of manufacturing the semiconductor device. The semiconductor device includes an oxide semiconductor layer including a channel formation region, and a source and drain regions which are provided so that the channel formation region is interposed therebetween and have lower resistance than the channel formation region. The channel formation region and the source and drain regions each include a crystalline region.
122 Citations
15 Claims
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1. A method of manufacturing a semiconductor device, comprising:
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forming a crystalline oxide semiconductor layer; forming a first insulating layer over the crystalline oxide semiconductor layer; forming a gate electrode over the crystalline oxide semiconductor layer with the first insulating layer positioned therebetween; forming a gate insulating layer by etching the first insulating layer with the gate electrode used as a mask until the crystalline oxide semiconductor layer is partly exposed; and forming a crystalline region containing nitrogen in the crystalline oxide semiconductor layer by performing nitrogen plasma treatment on the exposed part of the crystalline oxide semiconductor layer, wherein the crystalline oxide semiconductor layer is a c-axis aligned crystalline oxide semiconductor layer, and wherein after the step of forming the gate insulating layer edges of the gate electrode and edges of the gate insulating layer are aligned. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of manufacturing a semiconductor device, comprising:
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forming an oxide semiconductor layer; forming a first insulating layer over the oxide semiconductor layer; forming a crystalline oxide semiconductor layer by performing heat treatment on the oxide semiconductor layer; forming a gate electrode over the crystalline oxide semiconductor layer with the first insulating layer positioned therebetween; forming a gate insulating layer by etching the first insulating layer with the use of the gate electrode as a mask until the crystalline oxide semiconductor layer is partly exposed; forming a crystalline region containing nitrogen in the crystalline oxide semiconductor layer by performing nitrogen plasma treatment on the exposed part of the crystalline oxide semiconductor layer; forming a second insulating layer covering the crystalline oxide semiconductor layer and the gate electrode; forming, in the second insulating layer, openings in regions overlapping with a source region and a drain region; and forming, over the second insulating layer, a source electrode and a drain electrode respectively in contact with the source region and the drain region through the openings, wherein the crystalline oxide semiconductor layer is a c-axis aligned crystalline oxide semiconductor layer, and wherein after the step of forming the gate insulating layer edges of the gate electrode and edges of the gate insulating layer are aligned. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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