Semiconductor device and method of manufacturing the same

• US 10,192,990 B2
• Filed: 12/11/2014
• Issued: 01/29/2019
• Est. Priority Date: 06/10/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yokoi, Tomokazu, Yamane, Yasumasa
• Primary Examiner(s): Tran, Tony
• Application Number:
  US14/567,214
• Publication Number:
  US 20150091008A1
• Time in Patent Office: 1,510 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/20 Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

A transistor which includes an oxide semiconductor and is capable of high-speed operation and a method of manufacturing the transistor. In addition, a highly reliable semiconductor device including the transistor and a method of manufacturing the semiconductor device. The semiconductor device includes an oxide semiconductor layer including a channel formation region, and a source and drain regions which are provided so that the channel formation region is interposed therebetween and have lower resistance than the channel formation region. The channel formation region and the source and drain regions each include a crystalline region.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a crystalline oxide semiconductor layer;

forming a first insulating layer over the crystalline oxide semiconductor layer;

forming a gate electrode over the crystalline oxide semiconductor layer with the first insulating layer positioned therebetween;

forming a gate insulating layer by etching the first insulating layer with the gate electrode used as a mask until the crystalline oxide semiconductor layer is partly exposed; and

forming a crystalline region containing nitrogen in the crystalline oxide semiconductor layer by performing nitrogen plasma treatment on the exposed part of the crystalline oxide semiconductor layer,

wherein the crystalline oxide semiconductor layer is a c-axis aligned crystalline oxide semiconductor layer, and

wherein after the step of forming the gate insulating layer edges of the gate electrode and edges of the gate insulating layer are aligned.

2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a base insulating layer before forming the crystalline oxide semiconductor layer.

3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the base insulating layer and the step of forming the crystalline oxide semiconductor layer are performed without being exposed to the air.

4. The method of manufacturing a semiconductor device according to claim 1, wherein a heating temperature for the nitrogen plasma treatment is in the range of 100°

C. to 550°

C.

5. The method of manufacturing a semiconductor device according to claim 1, wherein the nitrogen plasma treatment is performed in a mixed gas of nitrogen and a rare gas.

6. The method of manufacturing a semiconductor device according to claim 1, wherein the crystalline oxide semiconductor layer comprises In, Ga, and Zn.

7. The method of manufacturing a semiconductor device according to claim 1, wherein a substrate temperature at the step of forming the crystalline oxide semiconductor layer is higher than or equal to 150 degrees centigrade and lower than or equal to 450 degrees centigrade.

8. A method of manufacturing a semiconductor device, comprising:

forming an oxide semiconductor layer;

forming a first insulating layer over the oxide semiconductor layer;

forming a crystalline oxide semiconductor layer by performing heat treatment on the oxide semiconductor layer;

forming a gate electrode over the crystalline oxide semiconductor layer with the first insulating layer positioned therebetween;

forming a gate insulating layer by etching the first insulating layer with the use of the gate electrode as a mask until the crystalline oxide semiconductor layer is partly exposed;

forming a crystalline region containing nitrogen in the crystalline oxide semiconductor layer by performing nitrogen plasma treatment on the exposed part of the crystalline oxide semiconductor layer;

forming a second insulating layer covering the crystalline oxide semiconductor layer and the gate electrode;

forming, in the second insulating layer, openings in regions overlapping with a source region and a drain region; and

forming, over the second insulating layer, a source electrode and a drain electrode respectively in contact with the source region and the drain region through the openings,

wherein the crystalline oxide semiconductor layer is a c-axis aligned crystalline oxide semiconductor layer, and

wherein after the step of forming the gate insulating layer edges of the gate electrode and edges of the gate insulating layer are aligned.

9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of forming a base insulating layer before forming the oxide semiconductor layer.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the base insulating layer and the step of forming the oxide semiconductor layer are performed without being exposed to the air.

11. The method of manufacturing a semiconductor device according to claim 8, wherein the heat treatment is performed at a temperature higher than or equal to 250°

C. and lower than or equal to 700°

C.

12. The method of manufacturing a semiconductor device according to claim 8, wherein a heating temperature for the nitrogen plasma treatment is in the range of 100°

C. to 550°

C.

13. The method of manufacturing a semiconductor device according to claim 8, wherein the nitrogen plasma treatment is performed in a mixed gas of nitrogen and a rare gas.

14. The method of manufacturing a semiconductor device according to claim 8, wherein the oxide semiconductor layer comprises In, Ga, and Zn.

15. The method of manufacturing a semiconductor device according to claim 8, wherein a substrate temperature at the step of forming the oxide semiconductor layer is higher than or equal to 150 degrees centigrade and lower than or equal to 450 degrees centigrade.