Current switching circuit

• US 10,193,507 B1
• Filed: 07/31/2017
• Issued: 01/29/2019
• Est. Priority Date: 07/31/2017
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Avci, Celal, Cavus, Bilal Tarik
• Primary Examiner(s): Choe, Henry
• Application Number:
  US15/665,010
• Publication Number:
  US 20190036492A1
• Time in Patent Office: 547 Days
• Field of Search: 330254, 330261, 330252
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 1/483 with field-effect transistors
• CPC Class Codes: H03F 2200/91 the amplifier has a current mode topology
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03G 1/0017 the device being at least one of the amplifying solid state elements of the amplifier
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03L 1/023 by using voltage variable capacitance diodes

Abstract

A wide range differential current switching circuit can operate across a wide range of input currents and across a broad range of frequencies. A first differential current source can include a first transistor and a second transistor. The first transistor receives a switching signal and provides an output current and at output node. The second transistor receives an inverted switching signal, the first transistor and the second transistor coupled to each other at a tail node. A current source provides an input current to the tail node. A third transistor can provide a boost current to the tail node while the first transistor is off.

Claims

1. A current switching circuit with current boosting for operation across a wider range of frequencies, the current switching circuit comprising:

a differential current switching circuit comprising;

a first transistor configured to receive a switching signal and to provide an output current to an output node;

a second transistor configured to receive an inverted switching signal, the first transistor and the second transistor coupled to each other at a tail node; and

a first current source configured to provide an input current to the tail node; and

a third transistor coupled to the tail node, wherein the third transistor is configured to provide a boost current from a second current source to the tail node while the first transistor is off.

2. The current switching circuit of claim 1, further comprising:

a fourth transistor;

wherein the third transistor, the fourth transistor, and the second current source are arranged as a second differential current switching circuit; and

wherein the third transistor is configured to receive an inverted boost switching signal and the fourth transistor is configured to receive a boost switching signal.

3. The current switching circuit of claim 1, wherein the third transistor is configured to receive an inverted boost switching signal that has substantially a same period as the switching signal.

4. The current switching circuit of claim 3, wherein the inverted boost switching signal has a different duty cycle than the switching signal such that the third transistor turns off before the first transistor turns on to prevent the boost current from flowing to the output lode.

5. The current switching circuit of claim 1, wherein:

each of the first transistor, the second transistor, and the third transistor is a bipolar junction transistor;

the collector of the first transistor is coupled to the output node; and

an emitter of the first transistor and an emitter of the second transistor are coupled to the tail node.

6. The current switching circuit of claim 1, wherein during each switching period, the third transistor is configured to provide the boost current to the tail node while the second transistor is on and to cease providing the boost current to the tail node prior to the second transistor turning off.

7. The current switching circuit of claim 1, wherein the boost current is within an order of magnitude of a maximum current level of the input current.

8. The current switching circuit of claim 1, wherein the first transistor and the second transistor are respectively sized such that the first transistor can operate at the first transistor'"'"'s maximum frequency when biased with a first current and the second transistor can operate the second transistor'"'"'s maximum frequency when biased with a second current that is greater than the first current.

9. The current switching circuit of claim 1, wherein the first transistor and the second transistor are arranged as a differential pair, and wherein the second transistor and the third transistor are configured as a cascode.

10. The current switching circuit of claim 1, wherein the current switching circuit is configured to bias the second transistor such that the second transistor switches faster than the first transistor, and the second transistor causes a switching speed of the first transistor to be increased.

11. A current switching circuit for providing an output current at an output node, the current switching circuit comprising:

a first differential current switching circuit comprising a first current source and configured to alternate between passing an input current through a first transistor and through a second transistor, wherein the first transistor is configured to provide the output current; and

a second differential current switching circuit comprising a second current source and configured to alternate between passing a boost current through a third transistor and through a fourth transistor, wherein the second differential current circuit is configured to bias the second transistor by passing the boost current through the third transistor while the input current is being passed through the second transistor.

12. The current switching circuit of claim 11, wherein a main switching signal provided to the first differential current switching circuit has substantially a same period as a boost switching signal provided to the second differential current switching circuit.

13. The current switching circuit of claim 12, wherein a duty cycle of the boost switching signal is different than a duty cycle of the main switching signal.

14. The current switching circuit of claim 11, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are bipolar transistors.

15. The current switching circuit of claim 11, wherein the boost current is isolated from the output node across an entire switching period of the current switching circuit.

20. The current switching circuit of claim 11, wherein the first transistor and the second transistor are coupled to each other at a tail node, and the third transistor is coupled to the tail node.

16. A method for increasing differential circuit switching speeds, the method comprising:

causing an input current from a first current source of a first differential current switching circuit to switch between flowing to an output node of the first differential current switching circuit and flowing away from the output node of the first differential current switching circuit; and

causing a boost current from a second current source of a second differential current switching circuit to switch between;

biasing the first differential current switching circuit while the input current is flowing to first differential current switching circuit; and

flowing away from the first differential current switching circuit;

wherein biasing the first differential current switching circuit causes a switching speed of the first differential current switching circuit to be increased.

17. The method of claim 16, wherein the boost current is provided to bias the first differential current switching circuit for a subset of time that enables a wider a range of currents to flow to the output node while the input current is switched at a fixed frequency.

18. The method of claim 16, further comprising providing the input current through the output node to a part of a digital to analog converter (DAC) circuit.

19. The method of claim 16, further comprising providing the input current through the output node to an operational amplifier.