Continuous time linear equalizer with two adaptive zero frequency locations

• US 10,193,515 B2
• Filed: 08/10/2018
• Issued: 01/29/2019
• Est. Priority Date: 03/08/2017
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Inphi Corporation
• Inventors: Nagulapalli, Rajasekhar, Forey, Simon, Mishra, Parmanand
• Primary Examiner(s): Nguyen, Patricia T
• Application Number:
  US16/101,301
• Publication Number:
  US 20180351524A1
• Time in Patent Office: 172 Days
• CPC Class Codes: H03F 1/086 with FET's
• CPC Class Codes: H03F 2203/45151 At least one resistor being added at the input of a dif amp
• CPC Class Codes: H03F 2203/45156 At least one capacitor being added at the input of a dif amp
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 2203/45424 the CMCL comprising a comparator circuit
• CPC Class Codes: H03F 2203/45458 the CSC comprising one or more capacitors
• CPC Class Codes: H03F 2203/45488 the CSC being a pi circuit and a capacitor being used at the place of the resistor
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45197 Pl types H03F3/45224, H03F3/45251 take precedence
• CPC Class Codes: H03F 3/45659 Controlling the loading circuit of the differential amplifier
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H03G 5/28 having semiconductor devices
• CPC Class Codes: H04L 2025/03445 Time domain
• CPC Class Codes: H04L 2025/03535 Variable structures
• CPC Class Codes: H04L 25/03012 operating in the time domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices

Abstract

The present invention is directed to electrical circuits. More specifically, embodiments of the presentation provide a CTLE module that includes a two compensation sections. A high-frequency zero RC section is in the source of the differential pair and close to the bias current source. A low-frequency zero section is coupled to an output terminal and configured outside the input signal path. A DC gain tuning section is coupled to the low-frequency zero section. There are other embodiments as well.

Claims

1. A linear equalizer device comprising:

a first input transistor comprising a first gate terminal a first drain terminal and a first source terminal, the first gate terminal being configured to receive a first input signal;

a second input transistor comprising a second gate terminal a second drain terminal and a second source terminal, the second gate terminal being configured to receive a second input signal;

a first compensation circuit coupled to the first drain terminal; and

a high-frequency zero circuit comprising at least a pair of source resistors and a pair of source capacitors;

wherein;

the pair of source resistors comprises a first source resistor coupled to the first source terminal and a second source resistor coupled to the first source resistor and the second source terminal, a first terminal being positioned between the first source resistor and the second source resistor;

the pair of source capacitors comprises a first source capacitor coupled to the first source terminal and a second source capacitor coupled to the second source terminal, a second terminal being positioned between the first source capacitor and the second source capacitor and coupled to the first terminal.

2. The device of claim 1 wherein the first input signal and the second input signal are a pair of differential input signals.

3. The device of claim 1 wherein the first source resistor and the first source capacitor are configured in parallel.

4. The device of claim 1 further comprising a bias current source coupled to the first source terminal.

5. The device of claim 1 wherein the first resistor comprises a variable resistor.

6. The device of claim 1 wherein the first resistor and the first capacitor are associated with a predetermined high-frequency zero.

7. The device of claim 1 further comprising a first gain tuning circuit coupled to the first compensation circuit, the first gain turning circuit comprising a first switch, the first switch being coupled to a control logic.

8. The device of claim 1 further comprising a pair of common mode resistors coupled to the first drain terminal.

9. The device of claim 1 wherein the first input transistor comprises an NMOS transistor.

10. The device of claim 1 wherein the first capacitor comprises a variable capacitor.

11. The device of claim 1 wherein the first compensation circuit comprises a first load capacitor and a first load resistor, the first load capacitor and the first load resistor being associated with a predetermined low-frequency zero.

12. The device of claim 1 wherein the first load resistor comprises a variable resistor.

13. The device of claim 12 further comprising:

a second compensation circuit coupled to the second drain terminal, the second compensation circuit comprising a second load capacitor and a second load resistor, the second load capacitor and the second load resistor being associated with the predetermined low-frequency zero;

a second gain tuning circuit coupled to the second compensation circuit.

14. The device of claim 13 further comprising:

a first common mode resistor coupled to the first drain terminal;

a second common mode resistor coupled to the second drain terminal, the second common mode resistor being characterized by a resistance value matching the first common mode resistor;

an operational amplifier coupled to the first common mode resistor and the second common mode resistor.

15. The device of claim 14 further comprising:

a first common transistor comprising a third gate terminal and a third source terminal and a third drain terminal, the third gate terminal being coupled to an output of the operation amplifier, the third terminal being coupled to the first compensation circuit;

a second common transistor comprising a fourth gate terminal and a fourth source terminal and a fourth drain terminal, the fourth gate terminal being coupled to the output of the operational amplifier.

16. The device of claim 15 further comprising a supply voltage coupled to the first load capacitor.

17. A receiver apparatus comprising:

a first input terminal;

a second input terminal;

a lost-of-signal detection circuit coupled to the first input terminal and the second input terminal; and

an equalizer circuit comprising;

a first input transistor comprising a first gate terminal a first drain terminal and a first source terminal, the first gate terminal being coupled to the first input signal;

a second input transistor comprising a second gate terminal a second drain terminal and a second source terminal, the second gate terminal being coupled to the second input signal;

a first source resistor coupled to the first source terminal;

a second source resistor coupled to the first source resistor and the second source terminal;

a first terminal positioned between the first source resistor and the second source resistor;

a first source capacitor coupled to the first source terminal;

a second source capacitor coupled to the second source terminal;

a second terminal positioned between the first source capacitor and the second source capacitor and coupled to the first terminal.

18. The apparatus of claim 17 further comprising:

a first compensation circuit coupled to the first drain terminal;

a second compensation circuit coupled to the second drain terminal;

a first gain tuning circuit coupled to the first compensation circuit;

a second gain tuning circuit coupled to the second compensation circuit;

a common mode operational amplifier coupled to the second compensation circuit.

19. A continuous-time linear equalizer device comprising:

a first input transistor comprising a first gate terminal a first drain terminal and a first source terminal, the first gate terminal being configured to receive a first input signal;

a second input transistor comprising a second gate terminal a second drain terminal and a second source terminal, the second gate terminal being configured to receive a second input signal;

a first common mode resistor coupled to the first drain terminal;

a high-frequency zero circuit comprising at least a pair of source resistors and a pair of source capacitors;

wherein;

the pair of source resistors comprises a first source resistor coupled to the first source terminal and a second source resistor coupled to the first source resistor and the second source terminal, a first terminal being positioned between the first source resistor and the second source resistor;

the pair of source capacitors comprises a first source capacitor coupled to the first source terminal and a second source capacitor coupled to the second source terminal, a second terminal being positioned between the first source capacitor and the second source capacitor and coupled to the first terminal.

20. The device of claim 19 further comprising:

a second common mode resistor coupled to the second drain terminal;

a common mode operational amplifier coupled to the first common resistor and the second common mode resistor.