Clock data recovery with decision feedback equalization

• US 10,193,716 B2
• Filed: 04/28/2017
• Issued: 01/29/2019
• Est. Priority Date: 04/28/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Hormati, Ali, Simpson, Richard
• Primary Examiner(s): Fan, Chieh M
• Assistant Examiner(s): Hailegiorgis, Fitwi
• Application Number:
  US15/582,545
• Publication Number:
  US 20170317859A1
• Time in Patent Office: 641 Days
• Field of Search: 375233, 375326, 375340
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 25/03949 equalizer selection or adaptation based on feedback multiple signaling inclusive of a precoding command for adapting the transmitter H04L1/0031; feedback for transmit diversity systems H04B7/0619; selection of codebook or precoding matrix for MIMO diversity systems H04B7/0456
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error indication, the phase error indication selected in response to identification of a predetermined data decision pattern.

Claims

1. A method comprising:

generating a received signal using a sub-channel detection multi-input comparator (MIC) operating on signals received via a plurality of wires, the signals received via the plurality of wires correspond to symbols of a codeword of a vector signaling code, the codeword corresponding to a weighted summation of a plurality of sub-channel vectors, each sub-channel vector mutually orthogonal;

generating two comparator outputs at a single sampling point by comparing the received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds associated with sub-channel specific inter-symbol interference on a multi-wire bus;

selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision; and

selecting one of the two comparator outputs as a phase-error indication to be provided to a clock recovery circuit generating the sampling clock in response to an identification of a predetermined data decision pattern.

2. The method of claim 1, further comprising adjusting a phase of the sampling clock according to the phase-error indication.

3. The method of claim 2, wherein the phase-error indication is an early/late logic decision on a transition of the received signal.

4. The method of claim 1, further comprising generating the first and second thresholds using a decision-feedback equalization (DFE) circuit.

5. The method of claim 4, wherein the first and second thresholds correspond to speculative DFE thresholds.

6. The method of claim 1, wherein the sub-channel specific ISI corresponds to modulation of components of a corresponding sub-channel vector associated with the received signal.

7. The method of claim 6, wherein sub-channel specific ISI associated with each sub-channel vector is mutually orthogonal.

8. The method of claim 1, further comprising filtering the received signal prior to generating the two comparator outputs.

9. An apparatus comprising:

a sub-channel detection multi-input comparator (MIC) operating on signals received via a plurality of wires, the sub-channel detection MIC configured to generate a received signal, wherein the signals received via the plurality of wires correspond to symbols of a codeword of a vector signaling code, the codeword corresponding to a weighted summation of a plurality of sub-channel vectors, each sub-channel vector mutually orthogonal;

two comparators configured to generate two comparator outputs at a single sampling time, the two comparators configured to compare the received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds associated with sub-channel specific inter-symbol interference on a multi-wire bus;

a data decision selection circuit configured to select one of the two comparator outputs as a data decision, the selection based on at least one prior data decision; and

a phase-error indication selection circuit configured to select one of the two comparator outputs in response to receiving a selection signal from a pattern detection circuit configured to identify a predetermined data decision pattern, and to responsively provide the selected comparator output to a clock recovery circuit as a phase-error indication.

10. The apparatus of claim 9, further comprising a receiver clock system configured to receive the phase-error indication and to responsively adjust a phase of the sampling clock.

11. The apparatus of claim 10, wherein the phase-error indication is an early/late logic decision on a transition of the received signal.

12. The apparatus of claim 9, further comprising a decision-feedback equalization (DFE) circuit configured to generate the first and second thresholds.

13. The apparatus of claim 12, wherein the first and second thresholds are speculative DFE thresholds.

14. The apparatus of claim 9, wherein the sub-channel specific ISI corresponds to modulation of components of a corresponding sub-channel vector associated with the received signal.

15. The apparatus of claim 14, wherein sub-channel specific ISI associated with each sub-channel vector is mutually orthogonal.

16. The apparatus of claim 9, further comprising a filter configured to filter the received signal prior to generating the two comparator outputs.