Microfabricated ultrasonic transducers and related apparatus and methods

• US 10,196,261 B2
• Filed: 03/08/2017
• Issued: 02/05/2019
• Est. Priority Date: 03/08/2017
• Status: Active Grant

• Current Assignee: BFLY Operations, Inc. (Butterfly Network, Inc.)
• Original Assignee: Butterfly Network, Inc.
• Inventors: Rothberg, Jonathan M., Alie, Susan A., Fife, Keith G., Sanchez, Nevada J., Ralston, Tyler S., Zahorian, Jaime Scott
• Primary Examiner(s): Kim, Su C
• Assistant Examiner(s): Wilbert, David S
• Application Number:
  US15/453,846
• Publication Number:
  US 20180257927A1
• Time in Patent Office: 699 Days
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: B06B 1/0622 on one surface
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 2201/038 Microengines and actuators not provided for in B81B2201/031 - B81B2201/037
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: B81C 1/00182 Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 2201/013 Etching
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H10N 30/01 Manufacture or treatment

Abstract

Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

Claims

1. An apparatus comprising:

a wafer comprising first and second silicon device layers;

a dielectric layer disposed between the first and second silicon device layers; and

a plurality of sealed cavities formed between the first and second silicon device layers, wherein a first sealed cavity of the plurality of sealed cavities comprises a recess in the first silicon device layer and extends through the dielectric layer disposed between the first and second silicon device layers, wherein a recessed surface of the recess in the first silicon device layer represents a first sealed end of the first sealed cavity.

2. The apparatus of claim 1, wherein the first and second silicon device layers are doped with at least 10¹⁵ dopants/cm³.

3. The apparatus of claim 1, further comprising a metallization layer electrically connected to the second silicon device layer through a bonding material.

4. The apparatus of claim 1, wherein the first sealed cavity comprises an outer cavity portion extending through the dielectric layer and in part through the first silicon device layer, and an inner cavity portion extending through the dielectric layer but not through the first silicon device layer.

5. The apparatus of claim 4, wherein the outer cavity portion has a greater depth than the inner cavity portion.

6. The apparatus of claim 4, wherein the outer cavity portion at least partially surrounds the inner cavity portion.

7. The apparatus of claim 6, wherein the outer cavity portion has a width that is between 100 nm and 500 μ

m.

8. The apparatus of claim 7, wherein the inner cavity portion has a width that is less than 400 μ

m.

9. The apparatus of claim 1, further comprising a clear out region extending through the first silicon device layer, the dielectric layer, and the second silicon device layer.

10. The apparatus of claim 1, further comprising a passivation layer disposed over the first silicon device layer and covering the first sealed cavity of the plurality of sealed cavities.