Semiconductor device

• US 10,197,627 B2
• Filed: 11/04/2014
• Issued: 02/05/2019
• Est. Priority Date: 11/07/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Primary Examiner(s): Nguyen, Tung X
• Application Number:
  US14/532,226
• Publication Number:
  US 20150123684A1
• Time in Patent Office: 1,554 Days
• CPC Class Codes: G01R 31/31813 Test pattern generators

Abstract

Provided is a semiconductor device which can generate a new test pattern even after design and have a reduced footprint of a circuit not used in normal operation. The semiconductor device includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a memory circuit that stores data and a plurality of circuits that make a signal for an operation test of the second integrated circuit. The signal is made when the continuity between the plurality of circuits is controlled by the memory circuit according to the data. In the second integrated circuit, the memory circuit is used as a buffer memory device after the operation test is conducted according to the signal.

Claims

1. A semiconductor device comprising:

a first circuit comprising a memory circuit; and

a second circuit,

wherein the first circuit is configured to store configuration data in the memory circuit to make a signal for an operation test of the second circuit, and

wherein the first circuit serves as a first set of a set associative buffer memory device of the second circuit after the operation test.

2. The semiconductor device according to claim 1,

wherein the first circuit comprises a first transistor and a second transistor, and

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor.

3. The semiconductor device according to claim 1,

wherein the first circuit comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor, and

wherein on/off of the second transistor is selected according to the data input through the first transistor.

4. The semiconductor device according to claim 1,

wherein the first circuit comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor, and

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

5. The semiconductor device according to claim 1,

wherein the first circuit comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein on/off of the second transistor is selected according to the data input through the first transistor, and

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

6. The semiconductor device according to claim 1,

wherein the first circuit comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor, and

wherein the oxide semiconductor comprises In, Ga, and Zn.

7. The semiconductor device according to claim 1,

wherein the first circuit comprises a first transistor and a second transistor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein on/off of the second transistor is selected according to the data input through the first transistor,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor, and

wherein the oxide semiconductor comprises In, Ga, and Zn.