Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework
First Claim
1. A method of generating a proximity-corrected design layout for photoresist to be used in an etch operation, the method comprising:
- (a) receiving an initial design layout;
(b) identifying a feature in the initial design layout, the feature'"'"'s pattern corresponding to a feature that would be etched into a material stack on a semiconductor substrate'"'"'s surface via a plasma-based etch process, performed in a processing chamber under a set of process conditions, when said material stack is overlaid with a layer of photoresist pattern corresponding to the initial design layout;
(c) estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature at a time t during such a plasma-based etch process;
(d) estimating a quantity characteristic of edge placement error (EPE) of the edge of the feature at time t by comparing the one or more quantities characteristic of the IFPF estimated in (c) to those in a look-up table (LUT) which associates values of the quantity characteristic of EPE at time t with values of the one or more quantities characteristics of the IFPF;
(e) modifying the initial design layout based on the quantity characteristic of EPE; and
(f) forming a mask based on a modified design layout produced in (e) and/or providing a photoresist on the material stack, wherein the photoresist contains a pattern based on the modified design layout,wherein the LUT was constructed by running a computerized etch profile model (EPM) under the set of process conditions at least to time t on a calibration pattern of photoresist overlaid on the material stack.
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Abstract
Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
69 Citations
32 Claims
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1. A method of generating a proximity-corrected design layout for photoresist to be used in an etch operation, the method comprising:
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(a) receiving an initial design layout; (b) identifying a feature in the initial design layout, the feature'"'"'s pattern corresponding to a feature that would be etched into a material stack on a semiconductor substrate'"'"'s surface via a plasma-based etch process, performed in a processing chamber under a set of process conditions, when said material stack is overlaid with a layer of photoresist pattern corresponding to the initial design layout; (c) estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature at a time t during such a plasma-based etch process; (d) estimating a quantity characteristic of edge placement error (EPE) of the edge of the feature at time t by comparing the one or more quantities characteristic of the IFPF estimated in (c) to those in a look-up table (LUT) which associates values of the quantity characteristic of EPE at time t with values of the one or more quantities characteristics of the IFPF; (e) modifying the initial design layout based on the quantity characteristic of EPE; and (f) forming a mask based on a modified design layout produced in (e) and/or providing a photoresist on the material stack, wherein the photoresist contains a pattern based on the modified design layout, wherein the LUT was constructed by running a computerized etch profile model (EPM) under the set of process conditions at least to time t on a calibration pattern of photoresist overlaid on the material stack. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A computer system for generating a proximity-corrected design layout for photoresist to be used in an etch operation, the system comprising:
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a processor, and a memory, the memory storing a look-up table (LUT) and computer-readable instructions for execution on the processor, including instructions for; (a) receiving an initial design layout; (b) identifying a feature in the initial design layout, the feature'"'"'s pattern corresponding to a feature that would be etched into a material stack on a semiconductor substrate'"'"'s surface via a plasma-based etch process, performed in a processing chamber under a set of process conditions, when said material stack is overlaid with a layer of photoresist pattern corresponding to the initial design layout; (c) estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature at a time t during such a plasma-based etch process; (d) estimating a quantity characteristic of edge placement error (EPE) of the edge of the feature at time t by comparing the one or more quantities characteristic of the IFPF estimated in (c) to those in the LUT which associates values of the quantity characteristic of EPE at time t with values of the one or more quantities characteristics of the IFPF; (e) modifying the initial design layout based on the quantity characteristic of EPE; and (f) forming a mask based on a modified design layout produced in (e) and/or providing a photoresist on the material stack, wherein the photoresist contains a pattern based on the modified design layout, wherein the LUT was constructed by running a computerized etch profile model (EPM) under the set of process conditions at least to time t on a calibration pattern of photoresist overlaid on the material stack. - View Dependent Claims (27, 29)
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28. One or more computer-readable media having a look-up table (LUT) and computer-readable instructions stored thereon, including instructions for:
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(a) receiving an initial design layout; (b) identifying a feature in the initial design layout, the feature'"'"'s pattern corresponding to a feature that would be etched into a material stack on a semiconductor substrate'"'"'s surface via a plasma-based etch process, performed in a processing chamber under a set of process conditions, when said material stack is overlaid with a layer of photoresist pattern corresponding to the initial design layout; (c) estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature at a time t during such a plasma-based etch process; (d) estimating a quantity characteristic of edge placement error (EPE) of the edge of the feature at time t by comparing the one or more quantities characteristic of the IFPF estimated in (c) to those in the LUT which associates values of the quantity characteristic of EPE at time t with values of the one or more quantities characteristics of the IFPF; (e) modifying the initial design layout based on the quantity characteristic of EPE; and (f) forming a mask based on a modified design layout produced in (e) and/or providing a photoresist on the material stack, wherein the photoresist contains a pattern based on the modified design layout, wherein the LUT was constructed by running a computerized etch profile model (EPM) under the set of process conditions at least to time t on a calibration pattern of photoresist overlaid on the material stack.
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30. A method of estimating a quantity characteristic of an edge placement error (EPE) of an edge of a feature on a semiconductor substrate having a design layout of photoresist overlaid on a material stack, the feature to be etched in a real or simulated plasma-based etch process performed in a correspondingly real or simulated processing chamber under a set of process conditions, the method comprising:
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(a) estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) at time t during the etch; (b) estimating the quantity characteristic of EPE at time t by comparing the one or more quantities characteristic of the IFPF estimated in (a) to those in a LUT which associates values of EPE at time t with one or more quantities characteristic of the IFPF; (c) modifying a design layout based on the quantity characteristic of EPE; and (d) forming a mask based on a modified design layout produced in (c) and/or providing a photoresist on the material stack, wherein the photoresist contains a pattern based on the modified design layout, wherein the LUT was constructed by running a computerized etch profile model (EPM) under the set of process conditions at least to time t on a calibration pattern of photoresist overlaid on the material stack. - View Dependent Claims (31, 32)
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Specification