Interleaved parallel circuit, integrated power module and integrated power chip

• US 10,198,020 B2
• Filed: 04/10/2017
• Issued: 02/05/2019
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Delta Electronics Shanghai Company Limited (Delta Electronics Incorporated)
• Original Assignee: Delta Electronics Shanghai Company Limited (Delta Electronics Incorporated)
• Inventors: Cai, Chaofeng, Liang, Le, Chen, Yan
• Primary Examiner(s): Jager, Ryan
• Application Number:
  US15/482,982
• Publication Number:
  US 20180059705A1
• Time in Patent Office: 666 Days
• Field of Search: 327540
• CPC Class Codes: G05F 3/20 using diode- transistor combinations G05F3/18 takes precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The present disclosure provides an interleaved parallel circuit, an integrated power module and an integrated power chip. The interleaved parallel circuit includes a first bridge arm and a second bridge arm at least partly formed in a wafer containing a plurality of first cell groups and a plurality of second cell groups. The plurality of first cell groups are configured to form the first upper bridge-arm switch and the plurality of second cell groups are configured to form the second upper bridge-arm switch, or the plurality of first cell groups are configured to form the first lower bridge-arm switch and the plurality of second cell groups are configured to form the second lower bridge-arm switch. The plurality of first cell groups and the plurality of second cell groups are switched on and off in an interleaved mode.

Claims

1. An interleaved parallel circuit comprising a first bridge arm and a second bridge arm, wherein

the first bridge arm comprises:

a first upper bridge-arm switch comprising a first terminal, a second terminal and a control terminal; and

a first lower bridge-arm switch comprising a first terminal, a second terminal and a control terminal;

wherein the second terminal of the first upper bridge-arm switch is electrically connected to the first terminal of the first lower bridge-arm switch;

the second bridge arm comprises;

a second upper bridge-arm switch comprising a first terminal, a second terminal and a control terminal; and

a second lower bridge-arm switch comprising a first terminal, a second terminal and a control terminal;

wherein the first bridge arm is connected in parallel with the second bridge arm;

the second terminal of the second upper bridge-arm switch is electrically connected to the first terminal of the second lower bridge-arm switch;

wherein the first bridge arm and the second bridge arm are at least partly formed in a wafer containing a plurality of first cell groups and a plurality of second cell groups;

wherein the plurality of first cell groups are configured to form the first upper bridge-arm switch of the first bridge arm and the plurality of second cell groups are configured to form the second upper bridge-arm switch of the second bridge arm; and

the plurality of first cell groups and the plurality of second cell groups are switched on and off alternatingly;

wherein the plurality of first cell groups are disposed in a first region of the wafer, and the plurality of second cell groups are disposed in a second region of the wafer;

wherein the first region contains a plurality of first sub-regions, and the second region contains a plurality of second sub-regions, each of the first sub-regions and the second sub-regions is in a stripe shape or a polygon shape, and the first sub-regions and the second sub-regions are arranged alternatively.

2. The interleaved parallel circuit according to claim 1, wherein the wafer is composed by the plurality of first cell groups and the plurality of second cell groups.

3. The interleaved parallel circuit according to claim 1, further comprising:

a first inductor comprising a first terminal and a second terminal, the first terminal of the first inductor being electrically connected to the second terminal of the first upper bridge-arm switch and the first terminal of the first lower bridge-arm switch; and

a second inductor comprising a first terminal and a second terminal, the first terminal of the second inductor being electrically connected to the second terminal of the second upper bridge-arm switch and the first terminal of the second lower bridge-arm switch;

wherein the second terminal of the first inductor is electrically connected to the second terminal of the second inductor.

4. The interleaved parallel circuit according to claim 1, wherein the plurality of first cell groups and the plurality of second cell groups are switched on and off alternatingly with a phase difference of 180 degrees, 120 degrees or 90 degrees.

5. The interleaved parallel circuit according to claim 1, wherein the plurality of first cell groups have a plurality of first external pins, the plurality of second cell groups have a plurality of second external pins, a geometric center of the plurality of first external pins overlaps with a geometric center of the plurality of second external pins.

6. The interleaved parallel circuit according to claim 1, wherein the interleaved parallel circuit is a BUCK circuit, a BOOST circuit or a Totem-Pole circuit.

7. An integrated power module, which is applied in an interleaved parallel circuit comprising a first bridge arm and a second bridge arm, wherein

the first bridge arm comprises:

a first upper bridge-arm switch comprising a first terminal, a second terminal and a control terminal; and

a first lower bridge-arm switch comprising a first terminal, a second terminal and a control terminal;

a first electrode electrically connected to the first terminal of the first upper bridge-arm switch;

a second electrode electrically connected to the second terminal of the first lower bridge-arm switch; and

a third electrode electrically connected to the second terminal of the first upper bridge-arm switch and the first terminal of the first lower bridge-arm switch;

the second bridge arm comprises;

a second upper bridge-arm switch comprising a first terminal, a second terminal and a control terminal, the first electrode being electrically connected to the first terminal of the second upper bridge-arm switch;

a second lower bridge-arm switch comprising a first terminal, a second terminal and a control terminal, the second electrode being electrically connected to the second terminal of the second lower bridge-arm switch; and

a fourth electrode electrically connected to the second terminal of the second upper bridge-arm switch and the first terminal of the second lower bridge-arm switch;

the integrated power module further comprises;

a first inductor comprising a first terminal and a second terminal, the first terminal of the first inductor being electrically connected to the third electrode; and

a second inductor comprising a first terminal and a second terminal, the first terminal of the second inductor being electrically connected to the fourth electrode;

wherein the second terminal of the first inductor is electrically connected to the second terminal of the second inductor;

the first upper bridge-arm switch of the first bridge arm and the second upper bridge-arm switch of the second bridge arm are formed in a wafer;

wherein the first upper bridge-arm switch of the first bridge arm and the second upper bridge-arm switch of the second bridge arm are formed in the wafer, the wafer contains a plurality of first cell groups and a plurality of second cell groups;

wherein the plurality of first cell groups are configured to form the first upper bridge-arm switch of the first bridge arm, the plurality of second cell groups are configured to form the second upper bridge-arm switch of the second bridge arm; and

the plurality of first cell groups and the plurality of second cell groups are switched on and off alternatingly;

wherein the plurality of first cell groups are disposed in a first region of the wafer, and the plurality of second cell groups are disposed in a second region of the wafer;

wherein the first region contains a plurality of first sub-regions, and the second region contains a plurality of second sub-regions, each of the first sub-regions and the second sub-regions is in a stripe shape or a polygon shape, and the first sub-regions and the second sub-regions are arranged alternatively.

8. The integrated power module according to claim 7, wherein the first lower bridge-arm switch of the first bridge arm and the second lower bridge-arm switch of the second bridge arm are formed in the wafer, the wafer contains a plurality of first cell groups and a plurality of second cell groups;

wherein the plurality of first cell groups are configured to form the first lower bridge-arm switch of the first bridge arm, the plurality of second cell groups are configured to form the second lower bridge-arm switch of the second bridge arm; and

the plurality of first cell groups and the plurality of second cell groups are switched on and off alternatingly.

9. The integrated power module according to claim 7, wherein the wafer is composed by the plurality of first cell groups and the plurality of second cell groups.

10. The integrated power module according to claim 8, wherein the wafer is composed by the plurality of first cell groups and the plurality of second cell groups.

11. An integrated power chip, which is applied in a power circuit comprising a first bridge arm and a second bridge arm, the first bridge arm comprising a first upper bridge-arm switch and a first lower bridge-arm switch, the second bridge arm comprising a second upper bridge-arm switch and a second lower bridge-arm switch, wherein

the integrated power chip comprises a first switch and a second switch, the first switch and second switch are formed in a wafer, and the wafer contains a plurality of first cell groups and a plurality of second cell groups;

wherein

the first bridge arm is connected in parallel with the second bridge arm;

the plurality of first cell groups are configured to form the first switch as the first upper bridge-arm switch of the first bridge arm and the plurality of second cell groups are configured to form the second switch as the second upper bridge-arm switch of the second bridge arm; and

the plurality of first cell groups and the plurality of second cell groups are switched on and off alternatingly;

wherein the plurality of first cell groups are disposed in a first region of the wafer, and the plurality of second cell groups are disposed in a second region of the wafer;

wherein the first region contains a plurality of first sub-regions, and the second region contains a plurality of second sub-regions, each of the first sub-regions and the second sub-regions is in a stripe shape or a polygon shape, and the first sub-regions and the second sub-regions are arranged alternatively.

12. The integrated power chip according to claim 11, wherein the wafer is composed by the plurality of first cell groups and the plurality of second cell groups.

13. An interleaved parallel circuit comprising a first bridge arm and a second bridge arm, wherein

the first bridge arm comprises:

a first upper bridge-arm switch comprising a first terminal, a second terminal and a control terminal; and

a first lower bridge-arm switch comprising a first terminal, a second terminal and a control terminal;

wherein the second terminal of the first upper bridge-arm switch is electrically connected to the first terminal of the first lower bridge-arm switch;

the second bridge arm comprises;

a second upper bridge-arm switch comprising a first terminal, a second terminal and a control terminal; and

a second lower bridge-arm switch comprising a first terminal, a second terminal and a control terminal;

wherein the first bridge arm is connected in parallel with the second bridge arm;

the second terminal of the second upper bridge-arm switch is electrically connected to the first terminal of the second lower bridge-arm switch;

wherein the first bridge arm and the second bridge arm are at least partly formed in a wafer containing a plurality of first cell groups and a plurality of second cell groups;

wherein the plurality of first cell groups are configured to form the first upper bridge-arm switch of the first bridge arm and the plurality of second cell groups are configured to form the second upper bridge-arm switch of the second bridge arm; and

the plurality of first cell groups and the plurality of second cell groups are switched on and off alternatingly;

wherein the plurality of first cell groups have a plurality of first external pins, the plurality of second cell groups have a plurality of second external pins, a geometric center of the plurality of first external pins overlaps with a geometric center of the plurality of second external pins.