Controlling power management in micro-server cores and peripherals

• US 10,198,060 B2
• Filed: 06/27/2016
• Issued: 02/05/2019
• Est. Priority Date: 03/31/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kumar, Anil K.
• Primary Examiner(s): Prifti, Aurel
• Application Number:
  US15/194,076
• Publication Number:
  US 20160306411A1
• Time in Patent Office: 953 Days
• Field of Search: 713323, 713300, 713320, 713324, 713228, 712220, 714 411
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/325 Power saving in peripheral device

Abstract

Systems and methods of enabling power management in a micro server include providing multiple cores, a power management module coupled to the cores, and one or more peripherals coupled to the power management module. The power management module may be configured to cause the one or more peripherals to delay operations based on determining that the cores are in a first power consumption state, and place the cores in a second power consumption state for a predetermined time period. The second power consumption state may consume less power than the first power consumption state. The power management module may cause the one or more peripherals to resume their operations based on expiration of the predetermined time period and may place the cores in a third power consumption state based on the expiration of the time period.

Claims

1. A computer-implemented method comprising:

using side band communication, causing one or more peripherals of a server having multiple cores to delay operations based on determining that the cores are being placed into a first power consumption state;

placing the cores into a second power consumption state during a time period, the second power consumption state consuming less power than the first power consumption state;

using the side band communication, causing the one or more peripherals to resume operations based on an expiration of the time period; and

placing the cores into a third power consumption state based on the expiration of the time period and based on receiving an indication that the one or more peripherals are unable to continue to delay their operations before the expiration of the time period, the third power consumption state consuming more power than the first power consumption state and the second power consumption state;

wherein the time period starts in response to the cores being placed into the first power consumption state;

wherein the time period is set based on a maximum direct memory access alignment period;

wherein the second power consumption state is a sleep-type power consumption state.

2. The method of claim 1, wherein the cores are associated with a first socket of a micro server having the first socket and a second socket.

3. The method of claim 2, wherein power consumption of cores associated with the second socket is configured independently of power consumption of the cores associated with the first socket.

4. The method of claim 1, wherein the sideband communications are conducted with a Gigabit Ethernet controller.

5. The method of claim 4, wherein the Gigabit Ethernet controller delays operations by aligning interrupts.

6. The method of claim 1, wherein the sideband communications are conducted with a Serial Advanced Technology Attachment (SATA) controller.

7. The method of claim 6, wherein the SATA controller delays operations by buffering data.

8. A system comprising:

multiple cores;

a power management unit coupled to the cores; and

one or more peripherals coupled to the power management unit, wherein the power management unit is to;

cause the one or more peripherals to delay operations based on determining that the cores are in a first power consumption state;

place the cores in a second power consumption state during a time period, the second power consumption state consuming less power than the first power consumption state;

cause the one or more peripherals to resume their operations based on expiration of the time period; and

place the cores in a third power consumption state based on the expiration of the time period and based on receiving an indication that the one or more peripherals are unable to continue to delay their operations before the expiration of the time period, the third power consumption state consuming more power than the first power consumption state and the second power consumption state;

wherein the time period starts in response to the cores being placed into the first power consumption state;

wherein the time period is set based on a maximum direct memory access alignment period;

wherein the second power consumption state is a sleep-type power consumption state.

9. The system of claim 8, wherein the power management unit is to communicate with the one or more peripherals using side band communications.

10. The system of claim 8, wherein the one or more peripherals include a Gigabit Ethernet controller, and wherein the Gigabit Ethernet controller is to delay operations by aligning interrupts.

11. The system of claim 8, wherein the one or more peripherals include a Serial Advanced Technology Attachment (SATA) controller, and wherein the SATA controller is to delay operations by buffering data.

12. The system of claim 8, wherein the cores are associated with a first socket of a micro server module having the first socket and a second socket.

13. The system of claim 12, wherein power consumption of cores associated with the second socket is to be configured independently of power consumption of the cores associated with the first socket.

14. The system of claim 13, wherein the first socket includes the cores and other socket components, and wherein power consumption of one or more of the other socket components of the first socket is to be reduced based on the cores being placed in the second power consumption state.

15. The system of claim 8, wherein the time period is to be programmable.

16. A non-transitory computer readable storage medium comprising a set of instruction which, when executed by a processor, cause a computer to:

using side band communication, cause one or more peripherals of a server having multiple cores to delay operations based on determining that the cores are being placed into a first power consumption state;

place the cores into a second power consumption state during a time period, the second power consumption state consuming less power than the first power consumption state;

using the side band communication, cause the one or more peripherals to resume operations based on an expiration of the time period; and

place the cores into a third power consumption state based on the expiration of the time period and based on receiving an indication that the one or more peripherals are unable to continue to delay their operations before the expiration of the time period, the third power consumption state consuming more power than the first power consumption state and the second power consumption state;

wherein the time period starts in response to the cores being placed into the first power consumption state;

wherein the time period is set based on a maximum direct memory access alignment period;

wherein the second power consumption state is a sleep-type power consumption state.

17. The medium of claim 16, wherein the cores are to be associated with a first socket of a micro server having the first socket and a second socket.

18. The medium of claim 17, wherein power consumption of cores associated with the second socket is to be configured independently of power consumption of the cores associated with the first socket.