Dynamic reconfiguration of multi-core processor
First Claim
1. A microprocessor, comprising a plurality of processing cores and a control unit having a plurality of registers, including a core sync register and a configuration register, which are used to control sleep states of the plurality of processing cores, wherein a disable instruction targeting any enabled one of the plurality of processing cores causes the targeted core to:
- interrupt the other cores with reconfiguration information stored in the configuration register, go into a sleep state, and stay in the sleep state until the other cores go into the sleep state; and
wake up after the other cores have gone into the sleep state and write a value to the control unit that causes the targeted core to become disabled, which is a condition, unlike the sleep state, in which the targeted core is unable to execute any more instructions until the microprocessor is reset, wherein the control unit outputs clock signals and power signals to each of the processor cores and the control unit controls the sleep state of the processing cores by selectively turning on or off the respective clock signals, wherein the control unit further controls the core power to each of the processing cores by selectively turning on or off the core power signals, and wherein a value in the core sync register is used by the control unit to control the sleep states of the respective processing cores.
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Accused Products
Abstract
A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.
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Citations
29 Claims
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1. A microprocessor, comprising a plurality of processing cores and a control unit having a plurality of registers, including a core sync register and a configuration register, which are used to control sleep states of the plurality of processing cores, wherein a disable instruction targeting any enabled one of the plurality of processing cores causes the targeted core to:
- interrupt the other cores with reconfiguration information stored in the configuration register, go into a sleep state, and stay in the sleep state until the other cores go into the sleep state; and
wake up after the other cores have gone into the sleep state and write a value to the control unit that causes the targeted core to become disabled, which is a condition, unlike the sleep state, in which the targeted core is unable to execute any more instructions until the microprocessor is reset, wherein the control unit outputs clock signals and power signals to each of the processor cores and the control unit controls the sleep state of the processing cores by selectively turning on or off the respective clock signals, wherein the control unit further controls the core power to each of the processing cores by selectively turning on or off the core power signals, and wherein a value in the core sync register is used by the control unit to control the sleep states of the respective processing cores. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
- interrupt the other cores with reconfiguration information stored in the configuration register, go into a sleep state, and stay in the sleep state until the other cores go into the sleep state; and
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14. A method for re-configuring a multi-core microprocessor having a plurality of processing cores and a control unit having a plurality of registers, including a core sync register and a configuration register, which are used to control sleep states of the plurality of processing cores, each processing core configured to receive a disable instruction, the method comprising the microprocessor responding to a disable instruction by:
- the core to whom the disable instruction is targeted interrupting the other cores with reconfiguration information stored in the configuration register, going into a sleep state, and staying in the sleep state unit the other cores to go into the sleep state;
the targeted core waking up after the other cores have gone into a sleep state and writing a value to the control unit that causes the targeted core to become disabled, which is a condition, unlike the sleep state, in which the targeted core is unable to execute any more instructions until the microprocessor is reset, wherein the control unit outputs clock signals and power signals to each of the processor cores and the control unit controls the sleep state of the processing cores by selectively turning on or off the respective clock signals, wherein the control unit further controls the core power to each of the processing cores by selectively turning on or off the core power signals, and wherein a value in the core sync register is used by the control unit to control the sleep states of the respective processing cores. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
- the core to whom the disable instruction is targeted interrupting the other cores with reconfiguration information stored in the configuration register, going into a sleep state, and staying in the sleep state unit the other cores to go into the sleep state;
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27. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:
- computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising first program code for specifying a plurality of processing cores and second program code for specifying a control unit having a plurality of registers, including a core sync register and a configuration register, which are used to control sleep states of the plurality of processing cores;
wherein a disable instruction targeting any enabled one of the plurality of processing cores causes the targeted core to;
interrupt the other cores with reconfiguration information stored in the configuration register, go into a sleep state until, and stay in the sleep state until the other cores go into the sleep state;
wake up after the other cores have gone into the sleep state and write a value to the control unit that causes the targeted core to become disabled, which is a condition that, unlike the sleep state, in which the targeted core is unable to execute any more instructions until the microprocessor is reset, wherein the control unit outputs clock signals and power signals to each of the processor cores and the control unit controls the sleep state of the processing cores by selectively turning on or off the respective clock signals, wherein the control unit further controls the core power to each of the processing cores by selectively turning on or off the core power signals, and wherein a value in the core sync register is used by the control unit to control the sleep states of the respective processing cores. - View Dependent Claims (28, 29)
- computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising first program code for specifying a plurality of processing cores and second program code for specifying a control unit having a plurality of registers, including a core sync register and a configuration register, which are used to control sleep states of the plurality of processing cores;
Specification