Dynamic reconfiguration of multi-core processor

• US 10,198,269 B2
• Filed: 05/19/2014
• Issued: 02/05/2019
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Parks, Terry, Gaskins, Darius D.
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Stewart, Kevin M
• Application Number:
  US14/281,657
• Publication Number:
  US 20150067310A1
• Time in Patent Office: 1,723 Days
• Field of Search: None
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

Claims

1. A microprocessor, comprising a plurality of processing cores and a control unit having a plurality of registers, including a core sync register and a configuration register, which are used to control sleep states of the plurality of processing cores, wherein a disable instruction targeting any enabled one of the plurality of processing cores causes the targeted core to:

interrupt the other cores with reconfiguration information stored in the configuration register, go into a sleep state, and stay in the sleep state until the other cores go into the sleep state; and

wake up after the other cores have gone into the sleep state and write a value to the control unit that causes the targeted core to become disabled, which is a condition, unlike the sleep state, in which the targeted core is unable to execute any more instructions until the microprocessor is reset, wherein the control unit outputs clock signals and power signals to each of the processor cores and the control unit controls the sleep state of the processing cores by selectively turning on or off the respective clock signals, wherein the control unit further controls the core power to each of the processing cores by selectively turning on or off the core power signals, and wherein a value in the core sync register is used by the control unit to control the sleep states of the respective processing cores.

2. The microprocessor of claim 1, wherein the configuration register is configured to indicate whether each of the processing cores is enabled or disabled;

wherein each enabled one of the plurality of processing cores is configured to;

read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled; and

generate a respective configuration-related value based on the read of the configuration register in the first instance;

wherein the configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled; and

wherein each enabled one of the plurality of processing cores is configured to;

read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled; and

generate the respective configuration-related value based on the read of the configuration register in the second instance.

3. The microprocessor of claim 2, wherein the respective configuration-related value comprises an indicator that indicates whether the processing core is a bootstrap processor of the microprocessor.

4. The microprocessor of claim 2, wherein the respective configuration-related value comprises a peripheral interrupt controller identifier associated with the processing core.

5. The microprocessor of claim 2 wherein the control unit is configured to wake up simultaneously each of the plurality of processing cores indicated by the configuration register as enabled in response to determining that each of the plurality of processing cores indicated by the configuration register as enabled has made a respective synchronization request and responsively been put to sleep.

6. The microprocessor of claim 5, wherein after the configuration register is updated to indicate that the previously enabled one of the plurality of processing cores is disabled, the control unit determines that each of the plurality of processing cores indicated by the configuration register as enabled has made a respective synchronization request and responsively been put to sleep.

7. The microprocessor of claim 2, wherein the microprocessor comprises a plurality of semiconductor dies;

wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies;

wherein the microprocessor includes an instance of the configuration register on each of the plurality of semiconductor dies; and

wherein each enabled one of the distinct subset of the plurality of processing cores located on each of the plurality of semiconductor dies is configured to read the instance of the configuration register on the semiconductor die.

8. The microprocessor of claim 7, wherein each instance of the configuration register is updated to indicate that the previously enabled one of the plurality of processing cores is disabled.

9. The microprocessor of claim 8, wherein the microprocessor includes an instance of the control unit on each of the plurality of semiconductor dies;

wherein each instance of the control unit is configured to determine that each of the plurality of processing cores indicated by the configuration register as enabled has made a respective synchronization request and responsively been put to sleep; and

wherein for each semiconductor die of the plurality of semiconductor dies, the instance of the control unit is configured to wake up simultaneously each enabled one of the distinct subset of the plurality of processing cores located on the semiconductor die indicated by the configuration register as enabled, in response to determining that each of the plurality of processing cores indicated by the configuration register as enabled has made a respective synchronization request and responsively been put to sleep.

10. The microprocessor of claim 2, wherein the configuration register is updated to indicate that the previously enabled one of the plurality of processing cores is disabled in response to the previously enabled processing core writing to a control register.

11. The microprocessor of claim 10, wherein the previously enabled processing core writes to the control register in response to executing an architectural instruction that instructs the previously enabled processing core to disable itself.

12. The microprocessor of claim 2, wherein each enabled one of the plurality of processing cores reads the configuration register in the first instance in response to a reset of the microprocessor.

13. The microprocessor of claim 2, wherein prior to the update of the configuration register, each enabled one of the plurality of processing cores performs the read of the configuration register in the second instance in response to the previously enabled processing core sending an interrupt request to each of the enabled one of the plurality of processing cores.

14. A method for re-configuring a multi-core microprocessor having a plurality of processing cores and a control unit having a plurality of registers, including a core sync register and a configuration register, which are used to control sleep states of the plurality of processing cores, each processing core configured to receive a disable instruction, the method comprising the microprocessor responding to a disable instruction by:

the core to whom the disable instruction is targeted interrupting the other cores with reconfiguration information stored in the configuration register, going into a sleep state, and staying in the sleep state unit the other cores to go into the sleep state;

the targeted core waking up after the other cores have gone into a sleep state and writing a value to the control unit that causes the targeted core to become disabled, which is a condition, unlike the sleep state, in which the targeted core is unable to execute any more instructions until the microprocessor is reset, wherein the control unit outputs clock signals and power signals to each of the processor cores and the control unit controls the sleep state of the processing cores by selectively turning on or off the respective clock signals, wherein the control unit further controls the core power to each of the processing cores by selectively turning on or off the core power signals, and wherein a value in the core sync register is used by the control unit to control the sleep states of the respective processing cores.

15. The method of claim 14, further comprising:

reading, by each enabled one of the plurality of processing cores, a configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled;

generating, by each enabled one of the plurality of processing cores, a respective configuration-related value based on said reading the configuration register in the first instance;

updating the configuration register to indicate that a previously enabled one of the plurality of processing cores is disabled;

reading, by each enabled one of the plurality of processing cores, the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled; and

generating, by each enabled one of the plurality of processing cores, the respective configuration-related value based on said reading the configuration register in the second instance.

16. The method of claim 15, wherein the respective configuration-related value comprises an indicator that indicates whether the processing core is a bootstrap processor of the microprocessor.

17. The method of claim 15, wherein the respective configuration-related value comprises a peripheral interrupt controller identifier associated with the processing core.

18. The method of claim 15, further comprising:

determining, by the control unit of the microprocessor, that each of the plurality of processing cores indicated by the configuration register as enabled has made a respective synchronization request and responsively been put to sleep; and

waking up, by the control unit, simultaneously each of the plurality of processing cores indicated by the configuration register as enabled, in response to said determining.

19. The method of claim 18, wherein said determining is performed by the control unit after said updating the configuration register to indicate that the previously enabled one of the plurality of processing cores is disabled.

20. The method of claim 15, wherein the microprocessor comprises a plurality of semiconductor dies;

wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies;

wherein the microprocessor includes an instance of the configuration register on each of the plurality of semiconductor dies; and

wherein said reading, by each enabled one of the plurality of processing cores, the configuration register comprises reading, by each enabled one of the distinct subset of the plurality of processing cores located on each of the plurality of semiconductor dies, the instance of the configuration register on the semiconductor die.

21. The method of claim 20, wherein said updating the configuration register to indicate that the previously enabled one of the plurality of processing cores is disabled comprises updating each instance of the configuration register.

22. The method of claim 21, wherein the microprocessor includes an instance of the control unit on each of the plurality of semiconductor dies, the method further comprising:

determining, by each instance of the control unit, that each of the plurality of processing cores indicated by the configuration register as enabled has made a respective synchronization request and responsively been put to sleep; and

waking up, by the instance of the control unit on each semiconductor die of the plurality of semiconductor dies, simultaneously each enabled one of the distinct subset of the plurality of processing cores located on the semiconductor die indicated by the configuration register as enabled, in response to said determining.

23. The method of claim 15, wherein said updating the configuration register to indicate that the previously enabled one of the plurality of processing cores is disabled is performed in response to the previously enabled processing core writing to a control register.

24. The method of claim 23, wherein said writing by the previously enabled processing core to the control register is performed by the previously enabled processing core in response to executing an architectural instruction that instructs the previously enabled processing core to disable itself.

25. The method of claim 15, wherein said reading the configuration register in the first instance is performed in response to a reset of the microprocessor.

26. The method of claim 15, wherein said reading, by each enabled one of the plurality of processing cores, the configuration register in the second instance is performed in response to the previously enabled processing core sending an interrupt request to each of the enabled one of the plurality of processing cores prior to said updating the configuration register to indicate that the previously enabled one of the plurality of processing cores is disabled.

27. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising first program code for specifying a plurality of processing cores and second program code for specifying a control unit having a plurality of registers, including a core sync register and a configuration register, which are used to control sleep states of the plurality of processing cores;

wherein a disable instruction targeting any enabled one of the plurality of processing cores causes the targeted core to;

interrupt the other cores with reconfiguration information stored in the configuration register, go into a sleep state until, and stay in the sleep state until the other cores go into the sleep state;

wake up after the other cores have gone into the sleep state and write a value to the control unit that causes the targeted core to become disabled, which is a condition that, unlike the sleep state, in which the targeted core is unable to execute any more instructions until the microprocessor is reset, wherein the control unit outputs clock signals and power signals to each of the processor cores and the control unit controls the sleep state of the processing cores by selectively turning on or off the respective clock signals, wherein the control unit further controls the core power to each of the processing cores by selectively turning on or off the core power signals, and wherein a value in the core sync register is used by the control unit to control the sleep states of the respective processing cores.

28. The computer program product of claim 27, the computer usable program code further comprising second program code for specifying a configuration register, configured to indicate whether each of the plurality of processing cores is enabled or disabled;

wherein each enabled one of the plurality of processing cores is configured to;

read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled; and

generate a respective configuration-related value based on the read of the configuration register in the first instance;

wherein the configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled; and

wherein each enabled one of the plurality of processing cores is configured to;

read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled; and

generate the respective configuration-related value based on the read of the configuration register in the second instance.

29. The computer program product of claim 28, wherein the at least one non-transitory computer usable medium is selected from the set of a disk, tape, or other magnetic, optical, or electronic storage medium.