Handling memory requests

• US 10,198,286 B2
• Filed: 03/28/2017
• Issued: 02/05/2019
• Est. Priority Date: 03/29/2016
• Status: Active Grant

• Current Assignee: Imagination Technologies Limited (Imagination Technologies Group Ltd.)
• Original Assignee: Imagination Technologies Limited (Imagination Technologies Group Ltd.)
• Inventors: Landers, Mark, Robinson, Martin John
• Primary Examiner(s): Bertram, Ryan
• Application Number:
  US15/471,256
• Publication Number:
  US 20170286151A1
• Time in Patent Office: 679 Days
• CPC Class Codes: G01N 33/0006 Calibrating gas analysers
• CPC Class Codes: G01N 33/0067 by measuring the rate of variation of the concentration
• CPC Class Codes: G01N 33/0073 Control unit therefor
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1063 the data cache being concurrently virtually addressed
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/684 TLB miss handling
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

Claims

1. A module comprising:

an assignment module arranged to receive memory requests from a cache and to assign a transaction identifier to each received memory request, wherein the memory requests received from the cache include one or more memory addresses defined in a virtual address space;

a transaction tracker module arranged to receive a memory request from the assignment module with the assigned transaction identifier, to track the status of the memory request and to receive translation information from a memory management unit, wherein the translation information comprises a translation of a virtual memory address in the memory request to a physical memory address or a pointer to the translation; and

an arbiter module arranged to receive a memory request from the transaction tracker module with the assigned transaction identifier when the memory request is ready for issue and to issue the memory request to a memory via an external bus and to trigger the freeing of the assigned transaction identifier in response to receiving a response from the memory via the external bus, wherein the memory request issued to memory includes one or more physical memory addresses determined using the translation information.

2. A module according to claim 1, wherein the arbiter module is further arranged to receive a plurality of memory requests and to select a memory request to issue from any received memory requests which have not yet been issued.

3. A module according to claim 2, wherein the arbiter module is further arranged to receive a memory read request from the memory management unit with a transaction identifier assigned by the memory management unit and to select the memory read request from the memory management unit for issue ahead of any memory requests received from the transaction tracker module which have not yet been issued.

4. A module according to claim 2, wherein the arbiter module is arranged to select a memory request to issue from any received memory requests which have not yet been issued according to pre-defined rules;

and optionally wherein the pre-defined rules cause the selection of a memory request received from the memory management unit ahead of a memory request received from the transaction tracker module and if there is not a memory request received from the memory management unit, selection of a memory request received from the transaction tracker module based at least in part on a time of receipt of the translation information for the memory requests.

5. A module according to claim 1, wherein the transaction identifiers assigned by the assignment module are external transaction identifiers and wherein the arbiter module is arranged to issue memory requests using the assigned external transaction identifiers.

6. A module according to claim 5, wherein the arbiter module is arranged, in response to receiving a response from the memory via the external bus, the response comprising an external transaction identifier, to identify the unit from which the corresponding request with the same external transaction identifier was received and to transmit the response to the identified unit, wherein the unit comprises the transaction tracker module or the memory management unit.

7. A module according to claim 1, wherein the transaction identifiers assigned by the assignment module are internal transaction identifiers and wherein the arbiter module is further arranged, following selection of a memory request for issue, to allocate an external transaction identifier to the memory request and store a mapping between the assigned internal transaction identifier and the allocated external transaction identifier and wherein the arbiter module is arranged to issue memory requests using the allocated external transaction identifiers.

8. A module according to claim 7, wherein the arbiter module is arranged, in response to receiving a response from the memory via the external bus, the response comprising an external transaction identifier, to map the external transaction identifier back to the assigned internal transaction identifier, identify the unit from which the corresponding request with the same internal transaction identifier was received and to transmit the response to the identified unit, wherein the unit comprises the transaction tracker module or the memory management unit.

9. A module according to claim 1, comprising a read path arranged to receive memory read requests from the cache and a write path arranged to receive memory write requests from the cache, wherein the read path comprises the assignment module, the transaction tracker module and the arbiter module and wherein the write path comprises a second assignment module, a second transaction tracker module and a second arbiter module.

10. A module according to claim 9, wherein the transaction tracker module and the second transaction tracker module are both arranged to check incoming memory requests from the cache for data hazards and in response to detecting a hazard, to set a flag for the incoming transaction and wherein a memory request is not ready for issue if the flag is set;

and optionally wherein the transaction tracker module and the second transaction tracker module are arranged to clear the flag for a memory request which depends upon an earlier memory request in response to receiving a response from the memory via the external bus for the earlier memory request.

11. A method comprising:

receiving memory requests from a cache at a converter module;

assigning, in the converter module, a transaction identifier to each received memory request, wherein the memory requests received from the cache include one or more memory addresses defined in a virtual address space;

tracking, in the converter module, the status of the memory requests;

receiving, in the converter module, translation information from a memory management unit, wherein the translation information comprises a translation of a virtual memory address in one of the memory requests to a physical memory address or a pointer to the translation;

issuing said one of the memory requests from the converter module to a memory via an external bus, wherein the memory request issued to memory includes one or more physical memory addresses determined using the translation information; and

triggering the freeing of the assigned transaction identifier in response to receiving a response from the memory via the external bus.

12. A method according to claim 11, further comprising:

selecting a memory request to issue from any received memory requests which have not yet been issued; and

optionally,

receiving a memory read request from the memory management unit with a transaction identifier assigned by the memory management unit, and wherein selecting a memory request comprises selecting a memory read request received from the memory management unit for issue ahead of any memory requests received from the cache.

13. A method according to claim 11, wherein a memory request is selected to issue according to pre-defined rules and optionally wherein the pre-defined rules cause the selection of a memory request received from the memory management unit ahead of a memory request received from the cache and if there is not a memory request received from the memory management unit, selection of a memory request received from the cache based at least in part on a time of receipt of the translation information for the memory requests.

14. A method according to claim 11, wherein the transaction identifiers assigned are external transaction identifiers and memory requests are issued using the assigned external transaction identifiers.

15. A method according to claim 11, wherein the transaction identifiers assigned are internal transaction identifiers and wherein the method further comprises, following selection of a memory request for issue:

allocating an external transaction identifier to the memory request; and

storing a mapping between the assigned internal transaction identifier and the allocated external transaction identifier,

and wherein memory requests are issued using the allocated external transaction identifiers.

16. A method according to claim 15, further comprising:

in response to receiving a response from the memory via the external bus, the response comprising an external transaction identifier, mapping the external transaction identifier back to the assigned internal transaction identifier.

17. A method according to claim 11, further comprising:

checking memory requests received from the cache for data hazards; and

in response to detecting a hazard, setting a flag for the incoming request and wherein a memory request cannot be issued if the flag is set.

18. A method according to claim 17, further comprising:

clearing a flag for a memory request which depends upon an earlier memory request in response to receiving a response from the memory via the external bus for the earlier memory request.

19. A system comprising:

a processor arranged to assign a transaction identifier to each memory request issued by the processor; and

a module comprising;

an assignment module arranged to receive memory requests from a cache, wherein the memory requests received from the cache include a transaction identifier assigned by the processor and one or more memory addresses defined in a virtual address space;

a transaction tracker module arranged to receive a memory request from the assignment module with the assigned transaction identifier, to track the status of the memory request and to receive translation information from a memory management unit, wherein the translation information comprises a translation of a virtual memory address in the memory request to a physical memory address or a pointer to the translation; and

an arbiter module arranged to receive a memory request from the transaction tracker module with the assigned transaction identifier when the memory request is ready for issue and to issue the memory request to a memory via an external bus and to trigger the freeing of the assigned transaction identifier in response to receiving a response from the memory via the external bus, wherein the memory request issued to memory includes one or more physical memory addresses determined using the translation information.

20. A method comprising:

assigning, in a processor, a transaction identifier to each issued memory request;

receiving memory requests from a cache at a converter module, wherein the memory requests received from the cache include a transaction identifier assigned by the processor and one or more memory addresses defined in a virtual address space;

tracking, in the converter module, the status of the memory request;

receiving, in the converter module, translation information from a memory management unit, wherein the translation information comprises a translation of a virtual memory address in the memory request to a physical memory address or a pointer to the translation;

issuing the memory request from the converter module to a memory via an external bus, wherein the memory request issued to memory includes one or more physical memory addresses determined using the translation information; and

triggering the freeing of the assigned transaction identifier in response to receiving a response from the memory via the external bus.