Display panel

• US 10,198,977 B2
• Filed: 07/23/2015
• Issued: 02/05/2019
• Est. Priority Date: 03/11/2015
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Seo, Sang Ho
• Primary Examiner(s): Laballe, Clayton E
• Assistant Examiner(s): Sanghera, Jas
• Application Number:
  US14/807,741
• Publication Number:
  US 20160267826A1
• Time in Patent Office: 1,293 Days
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A display panel is disclosed. In one aspect, the display panel includes a display unit including a plurality of pixels, an inspection circuit configured to apply a first inspection voltage to the display unit based on a first control signal, a pad portion electrically connected to the inspection circuit and configured to supply the first inspection voltage and the first control signal to the inspection circuit, and at least one external inspection line electrically connected between the inspection circuit and the pad portion. The external inspection line includes a plurality of transistors.

Claims

1. A display panel, comprising:

a display unit including a plurality of pixels;

an inspection circuit configured to apply a first inspection voltage to the display unit based on a first control signal;

a pad portion electrically connected to the inspection circuit and configured to supply the first inspection voltage and the first control signal to the inspection circuit; and

at least one external inspection line electrically connected between the inspection circuit and the pad portion,

wherein the external inspection line includes a plurality of transistors,

wherein the transistors of the external inspection line include a first transistor and a second transistor,

wherein the first transistor includes a first end electrically connected to a control terminal of the second transistor and a second end electrically connected to the pad portion, and

wherein the second transistor includes a first end electrically connected to the inspection circuit and a second end electrically connected to the pad portion.

2. A display panel, comprising:

a display unit including a plurality of pixels;

an inspection circuit configured to apply a first inspection voltage to the display unit based on a first control signal;

a pad portion electrically connected to the inspection circuit and configured to supply the first inspection voltage and the first control signal to the inspection circuit; and

at least one external inspection line electrically connected between the inspection circuit and the pad portion,

wherein the external inspection line includes a plurality of transistors,

wherein the transistors of the external inspection line include N transistors,

wherein an M-th transistor includes a first end electrically connected to the control terminal of an (M+1)-th transistor, a second end electrically connected to the pad portion, and a control terminal electrically connected to a first end of the (M−

1)-th transistor,

wherein an N-th transistor includes a first end electrically connected to the inspection circuit, a second end electrically connected to the pad portion, and a control terminal electrically connected to a first end of the (N−

1)-th transistor, and

wherein M and N are natural numbers, and wherein M is less than N and greater than 1.

3. The display panel of claim 2, wherein at least one of the N transistors is formed in a first region where a wire resistance of the external inspection line is greater than a predetermined resistance value.

4. The display panel of claim 3, wherein the transistor has a channel having a voltage drop amount less than a voltage drop amount due to the wire resistance in the first region.

5. The display panel of claim 2, wherein the display unit includes a plurality of data lines,

wherein the inspection circuit is electrically connected to the data lines and includes a plurality of inspection lines configured to supply the first inspection voltage, and

wherein the external inspection line is a selected one of a plurality of inspection lines, and wherein the external inspection line extends along an edge of the display panel.

6. The display panel of claim 5, wherein the inspection circuit is further configured to i) apply the first inspection voltage having a first level to the display unit when the first control signal has an ON-level so as to initialize the pixels and ii) apply the first inspection voltage having a second level to the display unit in the next ON-level of the first control signal such that the pixels emit light with a predetermined grayscale,

wherein one of the data lines that is electrically connected to the external inspection line is electrically connected to a pixel column including a group of pixels,

wherein the group of pixels in the pixel column is configured to not emit light with the predetermined grayscale when a crack exists on an edge of the display panel, and

wherein the first level is less than the second level.

7. The display panel of claim 6, wherein the pixel column is further configured to emit light with a grayscale corresponding to a voltage level between the first level and the second level when the crack exists and the first control signal has the next ON-level.

8. The display panel of claim 5, further comprising a data distribution circuit configured to receive a second inspection voltage and a second control signal front the pad portion and apply the second inspection voltage to the data lines based on the second control signal.

9. The display panel of claim 8, wherein the inspection circuit is further configured to apply the first inspection voltage to the display unit when the first control signal has the ON-level so as to initialize the pixels, wherein the data distribution circuit is further configured to apply the second inspection voltage to the display unit when the second control signal has the ON-level such that the pixels emit light with the predetermined grayscale,

wherein one of the data lines that is electrically connected to the external inspection line is electrically connected is to a pixel column including a group of pixels, and

wherein the group of pixels in the pixel column is configured to not emit light with the predetermined grayscale when a crack exists on an edge of the display panel, and

wherein the first level is less than the second level.

10. The display panel of claim 9, wherein the pixel column is further configured to emit light with a grayscale corresponding to a voltage level between the first inspection voltage and the second inspection voltage when the crack exists and the second control signal has the ON-level.

11. A display panel, comprising:

a display unit including a plurality of pixels;

an inspection circuit configured to apply a first inspection voltage to the display unit;

a pad portion electrically connected to the inspection circuit and configured to supply the first inspection voltage and a first control signal to the inspection circuit; and

a plurality of external inspection lines electrically connected between the inspection circuit and the pad portion, wherein a first one and a second one of the plurality of external inspection lines are respectively formed on left and right sides of the display unit,

wherein each of the plurality of external inspection lines includes a plurality of transistors, and wherein the plurality of the external inspection lines are configured to detect a crack on an edge of the display panel.

12. The display panel of claim 11, wherein each of the external inspection lines includes N transistors,

wherein an M-th transistor includes a first end electrically connected to a control terminal of an (M+1)-th transistor, a second end electrically connected to the pad portion, and an (M−

1)th transistor includes a first end connected to a control terminal of the M-th transistor,

wherein an N-th transistor includes a first end electrically connected to the inspection circuit, a second end electrically connected to the pad portion, and a control terminal electrically connected to a first end of the (N−

1)-th transistor, and

wherein M and N are natural numbers, and wherein M is less than N and greater than 1.

13. The display panel of claim 12, wherein the inspection circuit comprises a plurality of transistors each of which is connected to a column of pixels.

14. The display panel of claim 13, wherein the transistors of the first external inspection line are directly connected to one of the transistors of the inspection circuit, and wherein the second external inspection line is directly connected to different transistors of the inspection circuit.

15. The display panel of claim 12, wherein the display unit includes a plurality of data lines,

wherein the inspection circuit is electrically connected to the data lines and includes a plurality of inspection lines configured to supply the first inspection voltage, and

at least one of the plurality of inspection lines is connected to a selected external inspection line, wherein the selected external inspection line extends along an edge of the display panel.

16. The display panel of claim 15, further comprising a data distribution circuit configured to receive a second inspection voltage and a second control signal from the pad portion and apply the second inspection voltage to the data lines based on the second control signal.

17. The display panel of claim 16, wherein the data distribution circuit comprises a plurality of transistors each of which is connected to a column of pixels.

18. The display panel of claim 17, wherein at least a portion of the data distribution circuit is located on one of upper and lower sides of the display unit.

19. The display panel of claim 18, wherein at least a portion of the data distribution circuit is located on the other of the upper and lower sides of the display unit.