Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areas

• US 10,199,289 B1
• Filed: 03/31/2018
• Issued: 02/05/2019
• Est. Priority Date: 02/03/2015
• Status: Expired due to Fees

• Current Assignee: PDF Solutions
• Original Assignee: PDF Solutions
• Inventors: Lam, Stephen, Ciplickas, Dennis, Brozek, Tomasz, Cheng, Jeremy, Comensoli, Simone, De, Indranil, Doong, Kelvin, Eisenmann, Hans, Fiscus, Timothy, Haigh, Jonathan, Hess, Christopher, Kibarian, John, Lee, Sherry, Liao, Marci, Lin, Sheng-Che, Matsuhashi, Hideki, Michaels, Kimon, O'Sullivan, Conor, Rauscher, Markus, Rovner, Vyacheslav, Strojwas, Andrzej, Strojwas, Marcin, Taylor, Carl, Vallishayee, Rakesh, Weiland, Larg, Yokoyama, Nobuharu
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US15/942,485
• Time in Patent Office: 311 Days
• Field of Search: 257 48, 438 11- 18
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2027/11866 Gate electrode terminals or contacts
• CPC Class Codes: H01L 2027/11875 Wiring region, routing
• CPC Class Codes: H01L 2027/11888 More than 3 levels of metal
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 22/30 Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 27/11807 : CMOS gate arrays
• CPC Class Codes: H01L 28/00 : Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0684 : characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41725 : Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/45 : Ohmic electrodes

Abstract

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areas.

Claims

1. A method for processing a semiconductor wafer, comprising at least the following acts:

patterning a chamfer short-configured test area on the wafer;

patterning a first non-contact electrical measurement (NCEM) pad on the wafer;

patterning one or more connections to (i) electrically connect a first portion of the chamfer short-configured test area to the first NCEM pad and (ii) electrically connect a second portion of the chamfer short-configured test area to a permanent or virtual ground;

patterning a corner short-configured test area on the wafer;

patterning a second NCEM pad on the wafer;

patterning one or more connections to (i) electrically connect a first portion of the corner short-configured test area to the second NCEM pad and (ii) electrically connect a second portion of the corner short-configured test area to a permanent or virtual ground;

patterning a via open-configured test area on the wafer;

patterning a third NCEM pad on the wafer;

patterning one or more connections to (i) electrically connect a first portion of the via open-configured test area to the third NCEM pad and (ii) electrically connect a second portion of the via open-configured test area to a permanent or virtual ground;

obtaining one or more first inline non-contact electrical measurements (inline NCEMs) from the first NCEM pad, where each first inline NCEM provides a measurement indicative of a short or leakage in the chamfer short-configured test area;

obtaining one or more second inline NCEMs from the second NCEM pad, where each second inline NCEM provides a measurement indicative of a short or leakage in the corner short-configured test area; and

,

obtaining one or more third inline NCEMs from the third NCEM pad, where each third inline NCEM provides a measurement indicative of an open or resistance in the via open-configured test area.

2. A method for processing, as defined in claim 1, wherein obtaining the first, second, and third inline NCEMs involves using an e-beam inspector to obtain the NCEMs from the respective NCEM pads, by:

moving a stage in the inspector while scanning the respective NCEM pad; and

,

deflecting the inspector'"'"'s e-beam to account for motion of the stage during the scanning of the respective NCEM pad.

3. A method for processing, as defined in claim 1, wherein the acts of patterning the corner short-configured test area, patterning the second NCEM pad, and patterning the connections from/to the corner short-configured test area and the second NCEM pad are accomplished by instantiating a corner-short-configured or corner-leakage-configured, NCEM-enabled fill cell on the wafer.

4. A method for processing, as defined in claim 1, wherein the acts of patterning the via open-configured test area, patterning the third NCEM pad, and patterning the connections from/to the via open-configured test area and the third NCEM pad are accomplished by instantiating a via-open-configured or via-resistance-configured, NCEM-enabled fill cell on the wafer.

5. A method for processing, as defined in claim 1, further comprising using the first, second, and third inline NCEMs to determine whether to perform one or more additional processing steps in the continued processing of the wafer or other wafers currently being manufactured.

6. A method for processing, as defined in claim 1, further comprising using the first, second, and third inline NCEMs to determine whether to perform one or more additional inspection steps in the continued processing of the wafer or other wafers currently being manufactured.

7. A method for processing, as defined in claim 1, further comprising using the first, second, and third inline NCEMs to determine whether to perform one or more additional metrology steps in the continued processing of the wafer or other wafers currently being manufactured.

8. A method for processing, as defined in claim 1, further comprising using the first, second, and third inline NCEMs to determine whether to modify one or more processing steps in the continued processing of the wafer or other wafers currently being manufactured.

9. A method for processing, as defined in claim 1, further comprising using the first, second, and third inline NCEMs to determine whether to modify one or more inspection steps in the continued processing of the wafer or other wafers currently being manufactured.

10. A method for processing, as defined in claim 1, further comprising using the first, second, and third inline NCEMs to determine whether to modify one or more metrology steps in the continued processing of the wafer or other wafers currently being manufactured.

11. A method for processing, as defined in claim 1, wherein the first, second, and third NCEM pads are square, and obtaining each inline NCEM utilizes an e-beam with a square spot designed to match a footprint of the NCEM pads.

12. A method for processing, as defined in claim 1, wherein the first, second, and third NCEM pads each have an aspect ratio of greater than 3, and obtaining each inline NCEM utilizes an e-beam with a line-shaped spot.

13. A method for processing, as defined in claim 1, further comprising using the first, second, and third inline NCEMs to determine whether to continue or abandon processing of the wafer.

14. A method for processing, as defined in claim 1, wherein each of the first, second, and third NCEM pads is patterned within a scribe line area of the wafer.

15. A method for processing, as defined in claim 1, wherein each of the first, second, and third NCEM pads is patterned within a standard cell logic block.

16. A method for processing, as defined in claim 1, wherein the acts of patterning the chamfer short-configured test area, patterning the first NCEM pad, and patterning the connections from/to the chamfer short-configured test area and the first NCEM pad are accomplished by instantiating a chamfer-short-configured or chamfer-leakage-configured, NCEM-enabled fill cell on the wafer.

17. A method for processing, as defined in claim 16, that further comprises instantiating additional, differently configured, NCEM-enabled fill cells, said differently configured fill cells selected from a list that consists of:

tip-to-tip-short-configured, NCEM-enabled fill cells;

tip-to-tip-leakage-configured, NCEM-enabled fill cells;

tip-to-side-short-configured, NCEM-enabled fill cells;

tip-to-side-leakage-configured, NCEM-enabled fill cells;

side-to-side-short-configured, NCEM-enabled fill cells;

side-to-side-leakage-configured, NCEM-enabled fill cells;

L-shape-interlayer-short-configured, NCEM-enabled fill cells;

L-shape-interlayer-leakage-configured, NCEM-enabled fill cells;

diagonal-short-configured, NCEM-enabled fill cells;

diagonal-leakage-configured, NCEM-enabled fill cells;

corner-short-configured, NCEM-enabled fill cells;

corner-leakage-configured, NCEM-enabled fill cells;

interlayer-overlap-short-configured, NCEM-enabled fill cells;

interlayer-overlap-leakage-configured, NCEM-enabled fill cells;

via-chamfer-short-configured, NCEM-enabled fill cells;

via-chamfer-leakage-configured, NCEM-enabled fill cells;

merged-via-short-configured, NCEM-enabled fill cells;

merged-via-leakage-configured, NCEM-enabled fill cells;

snake-open-configured, NCEM-enabled fill cells;

snake-resistance-configured, NCEM-enabled fill cells;

stitch-open-configured, NCEM-enabled fill cells;

stitch-resistance-configured, NCEM-enabled fill cells;

via-open-configured, NCEM-enabled fill cells;

via-resistance-configured, NCEM-enabled fill cells;

metal-island-open-configured, NCEM-enabled fill cells;

metal-island-resistance-configured, NCEM-enabled fill cells;

merged-via-open-configured, NCEM-enabled fill cells; and

,

merged-via-resistance-configured, NCEM-enabled fill cells.

18. A method for processing, as defined in claim 1, wherein obtaining the first, second, and third inline NCEMs involves selectively targeting the first, second, and third NCEM pads, respectively.

19. A method for processing, as defined in claim 18, wherein obtaining each inline NCEM consists of measuring a single pixel from the respectively targeted NCEM pad.

20. A method for processing, as defined in claim 19, wherein obtaining each inline NCEM consists of averaging multiple, single-pixel measurements obtained from each respectively targeted NCEM pad.