Manufacturing methods of MOSFET-type compact three-dimensional memory

• US 10,199,432 B2
• Filed: 03/08/2017
• Issued: 02/05/2019
• Est. Priority Date: 04/14/2014
• Status: Active Grant

• Current Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Zarroli, Michael C
• Application Number:
  US15/453,866
• Publication Number:
  US 20170194379A1
• Time in Patent Office: 699 Days
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/021 Formation of switching materials, e.g. deposition of layers
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors

Abstract

Manufacturing methods of MOSFET-type compact three-dimensional memory (3D-M_C) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A MOSFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.

Claims

1. A manufacturing method of a MOSFET-type compact three-dimensional memory (3D-M_C) including a memory device and a decoding device, comprising the steps of:

1) forming a bottom electrode comprising a heavily doped semiconductor material on a memory level above a semiconductor substrate;

2) applying a photo-resist layer and forming a hole therein at the location of said decoding device but no hole at the location of said memory device;

3) ion-implanting through said hole in such a way that said heavily doped semiconductor material under said hole is counter-doped to a lightly doped semiconductor material; and

, said heavily doped semiconductor material under no hole remains heavily doped;

4) forming a memory/middle layer on top of said bottom electrode after removing said photo-resist layer;

5) etching said memory/middle layer and said bottom electrode together to define at least a x-line;

6) depositing and etching a top/gate electrode comprising a high-conductive material to define at least a y-line and a control-line (c-line);

wherein said memory device is formed at the intersection of said x-line and said y-line, and said decoding device is formed at the intersection of said x-line and said c-line.

2. The method according to claim 1, wherein the overlap portion and the non-overlap portions of said x-line with said y-line are both highly-conductive.

3. The method according to claim 1, wherein said memory device is a two-terminal device.

4. The method according to claim 1, wherein

the overlap portion of said x-line with said c-line is semi-conductive;

and,

the non-overlap portions of said x-line with said c-line are highly-conductive.

5. The method according to claim 1, wherein said decoding device is a three-terminal device.

6. The method according to claim 1, wherein said decoding device comprises a pass-transistor.

12. The method according to claim 1, wherein said decoding device is a three-terminal device.

13. The method according to claim 1, wherein said decoding device comprises a pass-transistor.

7. A manufacturing method of a MOSFET-type compact three-dimensional memory (3D-M_C) including a memory device and a decoding device, comprising the steps of:

1) forming a bottom electrode comprising a lower highly-conductive sub-layer and an upper semi-conductive sub-layer on a memory level above a semiconductor substrate;

2) applying a photo-resist layer and forming a hole therein at the location of said decoding device but no hole at the location of said memory device;

3) removing said highly-conductive sub-layer under said hole in such a way that said bottom electrode under said hole comprises only said semi-conductive sub-layer; and

, said bottom electrode under no hole comprises both said high-conductive sub-layer and said semi-conductive sub-layer;

4) forming a memory/middle layer on top of said bottom electrode after removing said photo-resist layer;

5) etching said memory/middle layer and said bottom electrode together to define at least a x-line;

6) depositing and etching a top/gate electrode comprising a high-conductive material to define at least a y-line and a control-line (c-line);

wherein said memory device is formed at the intersection of said x-line and said y-line, and said decoding device is formed at the intersection of said x-line and said c-line.

8. The method according to claim 7, wherein the overlap portion and the non-overlap portions of said x-line with said y-line are both highly-conductive.

9. The method according to claim 7, wherein the bottom electrode of said memory device comprises both said upper highly-conductive sub-layer and said lower semi-conductive sub-layer.

10. The method according to claim 7, wherein said memory device is a two-terminal device.

11. The method according to claim 7, wherein

the overlap portion of said x-line with said c-line is semi-conductive;

and,

the non-overlap portions of said x-line with said c-line are highly-conductive.

14. The method according to claim 7, wherein the bottom electrode of said decoding device comprises only said lower semi-conductive sub-layer.

15. A manufacturing method of a MOSFET-type compact three-dimensional memory (3D-M_C) including a memory device and a decoding device, comprising the steps of:

1) forming a bottom electrode comprising a metallic material on a memory level above a semiconductor substrate;

2) applying a photo-resist layer and forming a hole therein at the location of said decoding device but no hole at the location of said memory device;

3) replacing said highly-conductive material in said bottom electrode under said hole with a semi-conductive material;

4) forming a memory/middle layer on top of said bottom electrode after removing said photo-resist layer;

5) etching said memory/middle layer and said bottom electrode together to define at least a x-line;

6) depositing and etching a top/gate electrode comprising a high-conductive material to define at least a y-line and a control-line (c-line);

wherein said memory device is formed at the intersection of said x-line and said y-line, and said decoding device is formed at the intersection of said x-line and said c-line.

16. The method according to claim 15, wherein the overlap portion and the non-overlap portions of said x-line with said y-line are both highly-conductive.

17. The method according to claim 15, wherein said memory device is a two-terminal device.

18. The method according to claim 15, wherein

the overlap portion of said x-line with said c-line is semi-conductive;

and,

the non-overlap portions of said x-line with said c-line are highly-conductive.

19. The method according to claim 15, wherein said decoding device is a three-terminal device.

20. The method according to claim 15, wherein said decoding device comprises a pass-transistor.