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Manufacturing methods of MOSFET-type compact three-dimensional memory

  • US 10,199,432 B2
  • Filed: 03/08/2017
  • Issued: 02/05/2019
  • Est. Priority Date: 04/14/2014
  • Status: Active Grant
First Claim
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1. A manufacturing method of a MOSFET-type compact three-dimensional memory (3D-MC) including a memory device and a decoding device, comprising the steps of:

  • 1) forming a bottom electrode comprising a heavily doped semiconductor material on a memory level above a semiconductor substrate;

    2) applying a photo-resist layer and forming a hole therein at the location of said decoding device but no hole at the location of said memory device;

    3) ion-implanting through said hole in such a way that said heavily doped semiconductor material under said hole is counter-doped to a lightly doped semiconductor material; and

    , said heavily doped semiconductor material under no hole remains heavily doped;

    4) forming a memory/middle layer on top of said bottom electrode after removing said photo-resist layer;

    5) etching said memory/middle layer and said bottom electrode together to define at least a x-line;

    6) depositing and etching a top/gate electrode comprising a high-conductive material to define at least a y-line and a control-line (c-line);

    wherein said memory device is formed at the intersection of said x-line and said y-line, and said decoding device is formed at the intersection of said x-line and said c-line.

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