Method of manufacturing a semiconductor device having a charge compensation region underneath a gate trench

• US 10,199,456 B2
• Filed: 08/30/2016
• Issued: 02/05/2019
• Est. Priority Date: 11/26/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Jin, Minghao, Yip, Li Juin, Blank, Oliver, Vielemeyer, Martin, Hirler, Franz
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): Boulghassoul, Younes
• Application Number:
  US15/251,606
• Publication Number:
  US 20160372538A1
• Time in Patent Office: 889 Days
• Field of Search: 257341, 257331, 257330, 257333, 257332, 257328, 257329, 257327, 257335, 257340, 257339, 257342, 257409, 257509, 257510, 257513, 257514, 257607, 257365, 257492, 257493, 257262, 438259, 438587, 438212, 438525, 438270
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of forming a semiconductor device is provided. The device includes a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a semiconductor substrate comprising a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region, the second and third doped regions being formed in the first doped region, the second doped region extending from the main surface into the substrate, the third doped region interposed between the first and second doped regions beneath the main surface;

forming first and second field plate trenches vertically extending from the main surface to a bottom that is arranged in the first doped region;

forming first and second field plates arranged in the first and second field plate trenches, respectively, and being dielectrically insulated from the substrate;

forming a gate trench laterally arranged between the first and second field plate trenches and vertically extending from the main surface through the second and third doped regions so that the gate trench has a bottom arranged in the first doped region;

forming a gate electrode arranged in the gate trench and being dielectrically insulated from the substrate, the gate electrode being configured to control an electrically conductive channel in the third doped region; and

forming a compensation zone vertically extending from the bottom of the gate trench deeper into the first doped region,

wherein the compensation zone is laterally aligned with the gate trench along a cross-sectional plane of the device that is parallel to the main surface,

wherein the compensation zone is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface,

wherein the first and second doped regions have a first conductivity type,

wherein the third doped region and the compensation zone have a second conductivity type, and

wherein forming the compensation zone comprises;

implanting dopants through a sacrificial oxide layer at the bottom of the gate trench, and

wherein an oxide mask is provided on the main surface during the implanting of the dopants, wherein the dopants are substantially prevented from penetrating the main surface by the oxide mask.

2. The method of claim 1, wherein forming the gate trench comprises:

forming the oxide mask having a first thickness on the main surface; and

etching portions of the substrate that are uncovered by the oxide mask.

3. The method of claim 2, wherein forming the compensation zone comprises:

forming the sacrificial oxide layer at the bottom of the gate trench having a second thickness; and

implanting dopants through the sacrificial oxide layer while the oxide mask is arranged on the main surface,

wherein the first thickness is greater than the second thickness.

4. The method of claim 3, wherein the oxide mask is configured to form first and second lateral portions of the gate trench that are orthogonal to one another and form an intersection in the substrate, and wherein forming the compensation zone comprises:

covering the first and second lateral portions of the gate trench outside of the intersection during implanting of the dopants using a further mask such that the compensation zone is interrupted outside of the intersection.

5. The method of claim 1, wherein only the gate electrode and a gate dielectric are arranged in the gate trench, and wherein a bottom of the compensation zone is spaced closer to the main surface than the bottoms of the first and second field plate trenches.

6. The method of claim 1, further comprising:

forming third and fourth field plate trenches extending from the main surface to a bottom that is arranged in the first doped region; and

forming third and fourth field plates in the third and fourth field plate trenches, respectively, and being dielectrically insulated from the substrate,

wherein the gate electrode is laterally arranged between third and fourth field plate trenches from a plan view perspective of the main surface, and

wherein the compensation zone is arranged underneath a portion of the gate trench that is equidistant to the first, second, third and fourth field plates.

7. The method of claim 6, wherein the first, second, third and fourth field plate trenches each form a closed loop in a plane parallel to the main surface, wherein the first, second, third and fourth field plate trenches are collectively arranged in a rectangle, the rectangle being formed in the plane parallel to the main surface and being defined by center points of the closed loops, and wherein the portion of the gate trench that is equidistant to the first, second, third and fourth field plates is at a center of the rectangle.

8. The method of claim 7, wherein the gate trench comprises first and second lateral portions that form an intersection with one another at the center of the rectangle, and wherein the compensation zone extends from the bottom of the gate trench at the intersection.

9. The method of claim 8, wherein the first and second lateral portions of the gate trench are orthogonal to one another.

10. The method of claim 8, wherein the compensation zone is interrupted at regions of the substrate in which laterally adjacent ones of the first, second, third and fourth field plate trenches are closest to one another.

11. The method of claim 8, wherein the compensation zone extends from the bottom of the gate trench only at the intersection.

12. A method of forming a semiconductor device, the method comprising:

forming a semiconductor substrate comprising a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region, the second and third doped regions being formed in the first doped region, the second doped region extending from the main surface into the substrate, the third doped region interposed between the first and second doped regions beneath the main surface;

forming first and second field plate trenches vertically extending from the main surface to a bottom that is arranged in the first doped region;

forming first and second field plates arranged in the first and second field plate trenches, respectively, and being dielectrically insulated from the substrate;

forming a gate trench laterally arranged between the first and second field plate trenches and vertically extending from the main surface through the second and third doped regions so that the gate trench has a bottom arranged in the first doped region;

forming a gate electrode arranged in the gate trench and being dielectrically insulated from the substrate, the gate electrode being configured to control an electrically conductive channel in the third doped region;

forming a compensation zone vertically extending from the bottom of the gate trench deeper into the first doped region, and

forming a contact which extends through the gate trench and electrically couples the compensation zone to the second doped region, the contact being laterally adjacent to an end of the gate electrode,

wherein the compensation zone is laterally aligned with the gate trench along a cross-sectional plane of the device that is parallel to the main surface,

wherein the compensation zone is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface,

wherein the first and second doped regions have a first conductivity type,

wherein the third doped region and the compensation zone have a second conductivity type.