Transistor and method for forming the same
First Claim
1. A method for forming a transistor, comprising:
- forming a base structure, containing a first gate structure, an active layer covering the first gate structure, and an insulating structure in the active layer;
forming a second gate structure on the active layer;
forming a source-drain region, including a source region and a drain region in the active layer each on a different side of the second gate structure;
forming a first interlayer dielectric layer covering the base structure and the second gate structure;
forming a first contact hole that exposes the first gate structure by etching the first interlayer dielectric layer and the insulating structure;
forming a second contact hole that exposes the second gate structure and a third contact hole that exposes the drain region by etching the first interlayer dielectric layer; and
filling the first contact hole, the second contact hole, and the third contact hole with a conductive material to form a first plug structure, a second plug structure, and a third plug structure, that are aligned along a substantially same direction.
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Accused Products
Abstract
The present disclosure provides a method for forming a transistor, including: forming a base structure, containing a first gate structure, an active layer covering the first gate structure, and an insulating structure in the active layer; forming a second gate structure on the active layer; forming a source-drain region, including a source region and a drain region in the active layer each on a different side of the second gate structure; and forming a first interlayer dielectric layer covering the base structure and the second gate structure. The method also includes: forming a first contact hole that exposes the first gate structure by etching the first interlayer dielectric layer and the insulating structure; and forming a second contact hole that exposes the second gate structure and a third contact hole that exposes the drain region by etching the first interlayer dielectric layer.
8 Citations
20 Claims
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1. A method for forming a transistor, comprising:
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forming a base structure, containing a first gate structure, an active layer covering the first gate structure, and an insulating structure in the active layer; forming a second gate structure on the active layer; forming a source-drain region, including a source region and a drain region in the active layer each on a different side of the second gate structure; forming a first interlayer dielectric layer covering the base structure and the second gate structure; forming a first contact hole that exposes the first gate structure by etching the first interlayer dielectric layer and the insulating structure; forming a second contact hole that exposes the second gate structure and a third contact hole that exposes the drain region by etching the first interlayer dielectric layer; and filling the first contact hole, the second contact hole, and the third contact hole with a conductive material to form a first plug structure, a second plug structure, and a third plug structure, that are aligned along a substantially same direction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A transistor, comprising:
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a base structure, containing a first gate structure, an active layer covering the first gate structure, and an insulating structure in the active layer, the first gate structure including a gate-controlled portion and a connection portion; a second gate structure on the active layer, the first gate structure and the second gate structure sharing the active layer, wherein the gate-controlled portion is covered by the second gate structure and the connection portion is not covered by the second gate structure; a source-drain region, having a source region and a drain region in the active layer, each on a different side of two sides of the first gate structure and the second gate structure, wherein lightly doped regions (LDDs) are in the active layer on the two sides of the second gate structure, the lightly doped regions (LDDs) have same thickness as the source-drain region, the source-drain region each locates on a different side of two sides of the LDDs; a first interlayer dielectric layer covering the base structure and the second gate structure; a first plug structure, in the first interlayer dielectric layer and the insulating structure, being connected to the first gate structure; a second plug structure, in the first interlayer dielectric layer, being connected to the second gate structure; and a third plug structure, in the first interlayer dielectric layer, being connected to the drain region, wherein the first plug structure, the second plug structure, and the third plug structure being aligned along a substantially same direction, wherein the first plug structure, the second plug structure, and the third plug structure are perpendicular to a top surface of the first interlayer dielectric layer, and the first plug structure and the second plug structure are aligned in a direction perpendicular to a direction the second plug structure and the third plug structure are aligned. - View Dependent Claims (17, 18, 19, 20)
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Specification