Transistors incorporating metal quantum dots into doped source and drain regions

• US 10,199,505 B2
• Filed: 06/12/2017
• Issued: 02/05/2019
• Est. Priority Date: 09/25/2012
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Zhang, John H.
• Primary Examiner(s): Hall, Victoria K
• Application Number:
  US15/620,444
• Publication Number:
  US 20170278979A1
• Time in Patent Office: 603 Days
• Field of Search: 257 20, 438270
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/127 Quantum box structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/413 Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7781 : with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

Claims

1. A device, comprising:

a substrate having a first surface and a second surface opposite the first surface; and

a transistor that includes;

a gate in the substrate and positioned between the first and second surface of the substrate, the gate having a first surface that is coplanar with the first surface of the substrate;

a source region in the substrate and positioned between the first and second surface of the substrate, the source region having a first contact in the substrate, the source region having a first surface that is coplanar with the first surface of the substrate; and

a drain region in the substrate and positioned between the first and second surface of the substrate, the drain region having a second contact in the substrate, the drain region having a first surface that is coplanar with the first surface of the substrate.

2. The device of claim 1 wherein the gate extends into the substrate from the first surface towards the second surface by a first dimension and the first contact extends into the substrate from the first surface towards the second surface by a second dimension, the first dimension less than the second dimension.

3. The device of claim 1 wherein the source region extends into the substrate from the first surface towards the second surface by a first dimension and the first contact extends into the substrate from the first surface towards the second surface by a second dimension, the first dimension less than the second dimension.

4. The device of claim 1 wherein the drain region extends into the substrate from the first surface towards the second surface by a first dimension and the second contact extends into the substrate from the first surface towards the second surface by a second dimension, the first dimension greater than the second dimension.

5. The device of claim 1 wherein the first contact includes a metal quantum dot.

6. The device of claim 5 wherein the first contact has an octagon or hexagon shape at the first surface.

7. The device of claim 1 wherein the first contact has a square shape at the first surface.

8. The device of claim 1 wherein the gate includes a plurality of layers in the substrate, each of the layers of the plurality of layers having a surface coplanar with the first surface of the substrate.

9. The device of claim 1 wherein the first contact has a first surface that is coplanar with the first surface of the substrate and the source region surrounds sides of the first contact.

10. A device, comprising:

a substrate having a first surface, the substrate including;

a first doped region in the substrate and extending to a first depth from the first surface of the substrate; and

a second doped region in the substrate and extending to a second depth from the first surface of the substrate;

a gate in the substrate and extending to a third depth from the first surface of the substrate, a first surface of the gate being coplanar with the first surface of the substrate;

a first contact in the first doped region, the first contact having a fourth depth from the first surface of the substrate, the fourth depth being less than the first depth; and

a second contact in the second doped region, the second contact having a fifth depth from the first surface of the substrate, the fifth depth being less than the second depth.

11. The device of claim 10 wherein third depth is greater than the fourth and fifth depths.

12. The device of claim 11 wherein the third depth is less than the first and second depths.

13. The device of claim 10 wherein the first and second contacts are one of a circle, square, diamond, hexagon, and octagon shape at the first surface.

14. A device, comprising:

a substrate having a first surface and a second surface opposite the first surface;

a gate structure in the substrate, a first surface of the gate structure being coplanar with the first surface of the substrate, the gate structure including a gate dielectric;

a source region in the substrate, a first surface of the source region being coplanar with the first surface of the substrate;

a first contact in the source region, a first surface of the first contact being coplanar with the first surface of the substrate, a second surface of the first contact being closer to the second surface of the substrate than the gate dielectric is to the second surface of the substrate, the first surface of the first contact being opposite the second surface of the first contact;

a drain region in the substrate, a first surface of the drain region coplanar with the first surface of the substrate, the gate structure being between the source region and the drain region; and

a second contact in the drain region, a first surface of the second contact being coplanar with the first surface of the substrate, a second surface of the second contact being closer to the second surface of the substrate than the gate dielectric is to the second surface of the substrate, the first surface of the second contact being opposite the second surface of the second contact.

15. The device of claim 14 wherein the second surface of the first contact is closer to the second surface of the substrate than a second surface of the source region, the first surface of the source region being opposite the second surface of the source region, and the second surface of the second contact is closer to the second surface of the substrate than a second surface of the drain region, the first surface of the drain region being opposite the second surface of the drain region.

16. The device of claim 14 wherein the source region is in direct contact with the gate structure and the drain region is in direct contact with the gate structure.

17. The device of claim 14 wherein the first surface of the first contact has one of a circle, square, diamond, hexagon, and octagon shape.

18. The device of claim 14 wherein the first contact is between a first portion of the source region and a second portion of the source region.

19. The device of claim 14 wherein a second surface of the gate structure is closer to the second surface of the substrate than a second surface of the source region, the first surface of the gate structure being opposite the second surface of the gate structure and the first surface of the source region being opposite the second surface of the source region, a first portion of a sidewall of the gate structure contacts the source region and a second portion of the sidewall of the gate structure contacts the substrate.

20. The device of claim 14 wherein the gate structure has a first length and a first width at the first surface of the substrate, and the first contact has a second length and a second width in the same directions, the first length being greater than the second length and the first width being greater than the second width.