Semiconductor structure with stress-reducing buffer structure

• US 10,199,537 B2
• Filed: 12/28/2017
• Issued: 02/05/2019
• Est. Priority Date: 02/22/2014
• Status: Active Grant

• Current Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Inventors: Shatalov, Maxim S., Yang, Jinwei, Dobrinsky, Alexander, Shur, Michael, Gaska, Remigijus
• Primary Examiner(s): Ghyka, Alexander
• Application Number:
  US15/856,920
• Publication Number:
  US 20180122987A1
• Time in Patent Office: 404 Days
• Field of Search: None
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/145 with a current-blocking structure
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector

Abstract

A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.

Claims

1. A semiconductor structure comprising:

a substrate;

a buffer structure located adjacent to the substrate, the buffer structure including;

a buffer layer, wherein the buffer layer has a first side adjacent to the substrate, the first side including a plurality of islands of a first nitride-based material laterally separated from any other semiconductor material and a second side opposite the first side at which the islands are coalesced into a single layer of the first nitride-based material, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and

a set of semiconductor layers formed adjacent to the buffer structure, wherein the buffer structure is configured such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa.

2. The structure of claim 1, wherein the buffer structure further includes an intermediate layer formed of a second nitride-based material located immediately adjacent to the second side of the buffer layer.

3. The structure of claim 2, wherein the intermediate layer comprises a plurality of group III nitride semiconductor sub-layers.

4. The structure of claim 3, wherein the plurality of group III nitride semiconductor sub-layers include:

a nucleation sub-layer formed directly on the buffer layer, wherein the nucleation sub-layer includes a plurality of nucleation islands; and

a cavity containing sub-layer formed directly on the nucleation sub-layer, wherein the cavity containing sub-layer includes a plurality of cavities.

5. The structure of claim 4, wherein the plurality of group III nitride semiconductor sub-layers further include a coalescing semiconductor sub-layer formed directly on the cavity containing sub-layer.

6. The structure of claim 3, wherein the plurality of group III nitride semiconductor sub-layers further include:

a second nucleation sub-layer formed directly on the cavity containing sub-layer, wherein the second nucleation sub-layer includes a second plurality of nucleation islands; and

a second cavity containing sub-layer formed directly on the second nucleation sub-layer, wherein the second cavity containing sub-layer includes a second plurality of cavities.

7. The structure of claim 1, wherein the set of semiconductor layers includes:

an n-type layer located immediately adjacent to the buffer structure;

an active region located on a side of the n-type layer opposite the buffer structure; and

a p-type layer located on a side of the active region opposite the n-type layer.

8. The structure of claim 1, wherein a surface of the substrate adjacent to the buffer structure is patterned to form a set of protruding regions defined by a set of openings.

9. The structure of claim 8, further comprising a nucleation layer located between the substrate and the buffer structure, wherein the nucleation layer is formed directly on the set of protruding regions and the set of openings include areas with no semiconductor material.

10. The structure of claim 1, wherein the plurality of islands have an average size in a range between approximately 1 nanometer and approximately 100 nanometers and an average spacing in a range between approximately 10 nanometers and approximately 200 nanometers.

11. The structure of claim 1, wherein the plurality of islands have an average height in a range of approximately 5 Angstroms to approximately 100 Angstroms.

12. The structure of claim 1, wherein the buffer layer further includes a second plurality of islands located directly on the single layer, wherein the second plurality of islands are coalesced into a second single layer on a side opposite the single layer.

13. An optoelectronic device comprising:

a substrate;

a buffer structure located adjacent to the substrate, the buffer structure including;

a buffer layer, wherein the buffer layer has a first side adjacent to the substrate, the first side including a plurality of islands of a first semiconductor material laterally separated from any other semiconductor material and a second side opposite the first side at which the islands are coalesced into a single layer, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and

a set of semiconductor layers formed adjacent to the buffer structure, wherein the buffer structure is configured such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa, wherein the set of semiconductor layers include;

an n-type layer located on the buffer structure;

an active region located on a side of the n-type layer opposite the buffer structure; and

a p-type layer located on a side of the active region opposite the n-type layer.

14. The device of claim 13, wherein the active region is configured to emit ultraviolet radiation.

15. The device of claim 13, wherein the buffer structure further includes an intermediate layer located immediately adjacent to the second side of the buffer layer, wherein the intermediate layer includes a plurality of sub-layers, and wherein the plurality of sub-layers comprise a plurality of group III nitride semiconductor films having alternating tensile and compressive stresses.

19. The device of claim 13, wherein a surface of the substrate adjacent to the buffer structure is patterned to form a set of protruding regions defined by a set of openings.

20. The device of claim 19, further comprising a nucleation layer located between the substrate and the buffer structure, wherein the nucleation layer is formed directly on the set of protruding regions and the set of openings include areas with no semiconductor material.

16. An optoelectronic device comprising:

a substrate;

a nitride-based buffer structure located adjacent to the substrate, the buffer structure including;

a buffer layer, wherein the buffer layer has a first side including a plurality of islands of a first nitride-based semiconductor material laterally separated from any other semiconductor material and a second side opposite the first side at which the islands are coalesced into a single layer, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and

an intermediate layer located immediately adjacent to the second side of the buffer layer, wherein the intermediate layer comprises a plurality of group III nitride-based sub-layers; and

a set of group III nitride-based semiconductor layers formed adjacent to the intermediate layer, wherein the buffer structure has an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa, wherein the set of semiconductor layers include;

a group III nitride-based n-type layer located on the buffer structure;

a group III nitride-based active region located on a side of the n-type layer opposite the buffer structure, wherein the active region is configured to emit ultraviolet radiation; and

a group III nitride-based p-type layer located on a side of the active region opposite the n-type layer.

17. The device of claim 16, wherein the intermediate layer comprises a plurality of group III nitride sub-layers including:

a nucleation sub-layer formed directly on the buffer layer, wherein the nucleation sub-layer includes a plurality of nucleation islands; and

a cavity containing sub-layer formed directly on the nucleation sub-layer, wherein the cavity containing sub-layer includes a plurality of cavities.

18. The device of claim 16, wherein the n-type layer includes a plurality of interlayers, and wherein a frequency of the plurality of interlayers increases towards the active region.