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Semiconductor structure with stress-reducing buffer structure

  • US 10,199,537 B2
  • Filed: 12/28/2017
  • Issued: 02/05/2019
  • Est. Priority Date: 02/22/2014
  • Status: Active Grant
First Claim
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1. A semiconductor structure comprising:

  • a substrate;

    a buffer structure located adjacent to the substrate, the buffer structure including;

    a buffer layer, wherein the buffer layer has a first side adjacent to the substrate, the first side including a plurality of islands of a first nitride-based material laterally separated from any other semiconductor material and a second side opposite the first side at which the islands are coalesced into a single layer of the first nitride-based material, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and

    a set of semiconductor layers formed adjacent to the buffer structure, wherein the buffer structure is configured such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa.

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