Low capacitance analog switch or transmission gate
First Claim
1. An analog switch circuit, comprising:
- a first pass FET, including a gate coupled to a first control signal input, a first conduction terminal coupled to a signal input, a second conduction terminal coupled to a signal output, and a first body switchably coupled to a first bias voltage when the first pass FET is off, the first body also switchably coupled to at least one of the signal input or the signal output when the first pass FET is on, wherein the first body is separated from a first semiconductor region by an insulator, wherein the first semiconductor region provides a node that is local to the analog switch circuit and the first semiconductor region is coupled to, or driven to a voltage like that of, one of the signal input or the signal output.
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Abstract
A low capacitance n-channel analog switch circuit, a p-channel analog switch circuit, and a full CMOS transmission gate (T-gate) circuit are described. Resistive decoupling can be used to isolate the switch or T-gate from AC grounds, such as one or more switch control signal inputs or supply voltages. A semiconductor region that is separated from a body region of a pass field-effect transistor (FET) can be coupled to or driven to a voltage similar to the input voltage or other desired voltage to help reduce parasitic capacitance of the switch or T-gate. The switch or T-gate can have improved frequency bandwidth or frequency response. The switch can be useful in a programmable gain amplifier (PGA) or programmable gain instrumentation amplifier (PGIA) or other circuit in which excessive switch capacitance could degrade circuit performance.
22 Citations
21 Claims
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1. An analog switch circuit, comprising:
a first pass FET, including a gate coupled to a first control signal input, a first conduction terminal coupled to a signal input, a second conduction terminal coupled to a signal output, and a first body switchably coupled to a first bias voltage when the first pass FET is off, the first body also switchably coupled to at least one of the signal input or the signal output when the first pass FET is on, wherein the first body is separated from a first semiconductor region by an insulator, wherein the first semiconductor region provides a node that is local to the analog switch circuit and the first semiconductor region is coupled to, or driven to a voltage like that of, one of the signal input or the signal output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An analog switch circuit, comprising:
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a first pass FET, including a gate coupled to a first control signal input via a first gate decoupling resistor, a first conduction terminal coupled to a signal input, a second conduction terminal coupled to a signal output, and a first body switchably coupled to a first bias voltage; a second pass FET, including a gate coupled to a second control signal input via a second gate decoupling resistor, a first conduction terminal coupled to the signal input, a second conduction terminal coupled to the signal output, and a second body switchably coupled to a second bias voltage; and a local first semiconductor region separated from the first body by an insulator, wherein the first semiconductor region provides a node that is local to the analog switch circuit and the first semiconductor region is configured to be coupled to, or driven to a voltage like that of, one of the signal input or the signal output.
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15. A method of using at least a first pass FET for switchably passing or isolating an analog signal from a signal input to a signal output, the method comprising:
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decoupling a body of the first pass FET from a first bias voltage when the first pass FET is off; switchably coupling the body of the first pass FET to one of the signal input or the signal output when the first pass FET is on; and driving a local first semiconductor region, separated from the first body by an insulator, to a voltage like that of one of the signal input or the signal output. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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Specification