Systems and methods for signal detection and digital bandwidth reduction in digital phased arrays

• US 10,200,081 B2
• Filed: 02/13/2017
• Issued: 02/05/2019
• Est. Priority Date: 02/12/2016
• Status: Active Grant

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Snow, Trevor
• Primary Examiner(s): Varndell, Ross
• Application Number:
  US15/431,503
• Publication Number:
  US 20170324440A1
• Time in Patent Office: 722 Days
• CPC Class Codes: H01Q 3/2658 Phased-array fed focussing structure
• CPC Class Codes: H01Q 3/38 the phase-shifters being digital
• CPC Class Codes: H01Q 3/40 with phasing matrix
• CPC Class Codes: H04B 1/66 for reducing bandwidth of signals; for improving efficiency of transmission H04B1/68 takes precedence
• CPC Class Codes: H04B 7/043 using best eigenmode, e.g. beam forming or beam steering
• CPC Class Codes: H04B 7/0837 using pre-detection combining H04B7/0868 takes precedence
• CPC Class Codes: H04B 7/088 using beam selection

Abstract

Methods and systems are provided including a system for signal detection and digital bandwidth reduction in a phased array comprising a digital phased array receiving system, digital beamforming network, and central system-level processing system. In at least one embodiment, a system for signal detection and digital bandwidth reduction in a phased array is provided that includes a digital phased array receiving and transmitting system, a plurality of digital processing nodes, transceivers, and a core processing node, and a plurality of digital beamforming nodes. The exemplary the digital processing nodes including control sections that each perform preprocessing to identify signals with predetermined signal characteristics. The exemplary said preprocessing further includes selecting reflected signals received by the digital phased array receiving and transmitting system having one or more of the predetermined signal characteristics. The selected reflected signals reduced in size and passed to the core processing node with radar data sets.

Claims

1. A system for signal detection and reduction of digital bandwidth into a digital beamformer, comprising:

a digital phased array receiving and transmitting system;

a plurality of digital processing nodes and transceivers;

a core processing node, and

a digital beamformer comprising at least one digital beamforming node;

wherein said digital processing nodes including control sections that store digitized received signals and perform a pre-detection process on digitized received signals with predetermined signal characteristics to form detection indicators with respect to time samples and based on a first threshold;

wherein said core processing node further comprises a binary integration circuit that counts said detection indicators from said digital processing nodes with respect to time to form a binary count vector, wherein said binary integration circuit compares said detection indicators to a second threshold, said binary integration circuit requests said stored digitized receive signals from said digital processing nodes within a predetermined time window before or after time samples passing the said second threshold; and

requested digitized receive signals are forwarded to said digital beamforming network, wherein said at least one digital beamforming node forms receive beam output data from said digitized receive signals.

2. A digital phased array system including a system for engaging in signal detection and reduction of digital bandwidth into a digital beamformer, comprising:

a core processing node;

a control network;

a transceiver section comprising a plurality of transceiver elements; and

a digital phased array transmitting and receiving system comprising a digital beamforming network and a signal processing section, the digital phased array and receiving system further comprises a plurality of connected digital beamforming nodes each comprising a waveform generator, a digital-to-analog-converter (DAC) or group of DACs, a set of analog-to-digital converters (ADC), a matched filter circuit, a sample storage circuit, a threshold detector, a binary integration circuit, a system-level coherent detection circuit, and a radar processing function element;

wherein the digital beamforming and signal processing section'"'"'s waveform generator creates a digital pulse waveform that is sent to the DAC or group of DACs that converts the digital pulse waveform into an analog signal, the analog signal is then sent to the transceiver that converts and amplifies the analog signal for transmission out of a connected antenna element;

wherein received signals from one or more transceiver elements are converted to a valid input range for said set of said analog-to-digital converters (ADC);

wherein digital samples from each ADC are transmitted to said matched filter circuit that applies pulse compression to maximize signal to noise ratio if a reflected transmit pulse is in a signal received by the transceiver and stores the result in the sample storage circuit;

wherein the threshold detector extracts time sample outputs from the sample storage and logs which time samples exceed a threshold, wherein a data word indicator of which time samples exceeded the threshold is sent to the binary integration circuit which receives similar indicators from other said threshold detectors in other digital beamforming nodes;

wherein the binary integration circuit counts detections in each time sample across all received indicators and declares a binary integration detection if the count exceeds another different threshold;

wherein a central controller requests filtered complex sample data from each sample storage circuit in each digital node for each time sample with a binary integration detection;

wherein the filtered complex sample data is sent through the network of connected digital beamforming nodes which apply weights to the filtered complex sample data and sum weighted data to form a number of electronically scanned receive beam data channels that correspond to signals received by an array of transceivers and connected antennas in said digital array;

wherein the system-level coherent detection circuit applies a new threshold detection to each sample on each received beam channel whose signal to noise ratio (SNR) is now increased or decreased if a signal is present and its direction of arrival corresponds to a high or low gain direction of an electronically scanned receive beam, wherein the coherent detection circuit applies threshold detection to samples in each received beam data channel and coherent detections exceeding a specified magnitude are sent to a radar signal processing section.

3. A digital phased array transmitting and receiving system for signal detection and reduction of digital bandwidth into a digital beamformer, comprising:

an array of antenna elements;

one or more transceivers;

one or more digital processing nodes;

a core processing node, and

a digital beamformer comprising at least one digital beamforming node;

wherein said transceivers are coupled to said one or more digital processing nodes and one or more antenna element of said array of antenna elements, and are configured to amplify received signals and transmit signals between said coupled one or more digital processing nodes and said coupled one or more antenna elements;

wherein said one or more digital processing nodes include one or more analog to digital converter (ADC) modules that are selectively coupled to one of the one or more transceivers transceiver and are configured to convert said received signals to sampled received signals and sampled transmit signals to transmit signals;

wherein said one or more digital processing nodes include a filter circuit coupled to said ADC configured to amplify said sampled received signals having predetermined signal characteristics and adapted to perform matched filtering on said sampled receive signals;

wherein said one or more digital processing nodes include a sample storage circuit configured to store said sampled receive signals when coupled to said ADC modules, and configured to store outputs from said filter circuit when coupled to said filter circuit;

wherein said one or more digital processing nodes further include a threshold detection module configured to analyze one or more signal parameters of said sampled received signals and determine if said signal parameters of said received signals exceed a first threshold for each of the one or more signal parameters on a prescribed time interval, forming positive first threshold detection indicators for each said signal parameter exceeding the associated said first threshold for said time sample within a sequence of time samples;

wherein said control node includes a binary integration circuit which is coupled to said threshold detection modules through a data network and is configured receive said first threshold detection indicators from said first threshold detectors and also configured to form a count of the occurrences of positive first threshold detection indicators across one or more said threshold detection modules for each said time sample within said sequence of time samples;

wherein said binary integration circuit is further configured to perform a second threshold detection based on said count and one or more second threshold parameters, forming a binary detection indicator for each said count passing the said second threshold detection at each said time sample;

wherein said binary integration circuit is further coupled to a central controller configured to process said binary detection indicators and send request commands for said stored receive signal data to a coupled node controller within each of the said one or more digital processing nodes via a control network;

wherein said at least one digital beamforming node is coupled to said sample storage circuits via a data network and are configured to receive said requested stored receive signal data and further apply digital weights to form receive beam output data from stored receive signal data.