Process for manufacturing a semiconductor device including a microelectromechanical structure and an associated integrated electronic circuit and corresponding semiconductor device

• US 10,202,275 B2
• Filed: 03/07/2017
• Issued: 02/12/2019
• Est. Priority Date: 08/09/2016
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Tocchio, Alessandro, Corso, Lorenzo
• Primary Examiner(s): Chang, Jay C
• Application Number:
  US15/452,424
• Publication Number:
  US 20180044168A1
• Time in Patent Office: 707 Days
• Field of Search: None
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2207/092 Buried interconnects in the substrate or in the lid
• CPC Class Codes: B81B 2207/096 through the substrate
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2201/0132 Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/0136 Growing or depositing of a covering layer
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure

Abstract

A process for manufacturing an integrated semiconductor device, envisages: forming a MEMS structure; forming an ASIC electronic circuit; and electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.

Claims

1. A process for manufacturing an integrated semiconductor device, comprising:

forming a micro-electro-mechanical system (MEMS) structure on a first surface of a substrate including semiconductor material, wherein forming said MEMS structure comprises carrying out first processing steps of forming said MEMS structure at said first surface;

forming an application specific integrated circuit (ASIC) electronic circuit on a second surface of said substrate, vertically opposite to said first surface, in a direction transverse to a horizontal plane of extension of said first surface;

electrically coupling said MEMS structure to said ASIC electronic circuit;

after carrying out said first processing steps, bonding a first service wafer over said MEMS structure, and vertically flipping said substrate, wherein forming the ASIC electronic circuit occurs after vertically flipping said substrate, wherein electrically coupling said MEMS structure to said ASIC electronic circuit comprises forming interconnection structures, which extend vertically through a first portion of said substrate starting from said first surface; and

removing a second portion of said substrate, vertically opposite to said first portion, so as to define said second surface and to make said interconnection structures accessible at said second surface, said interconnection structures thereby having a first end at said first surface and a second end at said second surface;

wherein forming said ASIC electronic circuit is performed at said second surface after removing said second portion of said substrate.

2. The process according to claim 1, wherein electrically coupling said MEMS structure to said ASIC electronic circuit further comprises forming at least one conductive path between the second end of at least one of said interconnection structures and at least one conductive element of said ASIC electronic circuit.

3. The process according to claim 1, wherein removing said second portion of said substrate is carried out after said flipping step.

4. The process according to claim 3, further comprising, after forming said ASIC electronic circuit, bonding a second service wafer over said ASIC electronic circuit and once again flipping said substrate;

and wherein forming said MEMS structure further comprises, after said step of once again flipping said substrate;

removing said first service wafer from said first surface; and

carrying out second processing steps of said MEMS structure.

5. The process according to claim 4, wherein said first, or second, processing steps of said MEMS structure comprise forming at least one conductive path between the first end of at least one of said interconnection structures and at least one element of said MEMS structure.

6. The process according to claim 4, wherein said first processing steps comprise forming a sacrificial layer over said first surface and forming an epitaxial layer on said sacrificial layer;

and wherein said second processing steps comprise forming through openings through said epitaxial layer, and carrying out a chemical etch that removes said sacrificial layer and defines at least one suspended element above said substrate.

7. The process according to claim 4, wherein said first processing steps comprise forming at least one buried cavity within the surface portion of said substrate, a membrane suspended above the buried cavity, and piezoresistive elements in said membrane;

and wherein said second processing steps comprise forming said conductive path between the first end of at least one of said interconnection structures and at least one of said piezoresistive elements of said MEMS structure.

8. The process according to claim 1, wherein forming said ASIC electronic circuit comprises forming a complementary metal oxide semiconductor (CMOS) multilayer over said second surface.

9. The process according to claim 1, wherein:

said substrate is of a silicon on insulator (SOI) type, and

said surface portion is an active layer of the SOI substrate.

10. The process according to claim 1, further comprising coupling a covering over said MEMS structure.

11. A process for manufacturing an integrated semiconductor device, comprising:

forming a micro-electro-mechanical system (MEMS) structure on or in a first surface of a semiconductor layer;

forming an application specific integrated circuit (ASIC) electronic circuit on or in a second surface of the semiconductor layer, vertically opposite to said first surface, in a direction transverse to a horizontal plane of extension of said first surface; and

forming interconnection structures that extend vertically through the semiconductor layer and electrically couple the MEMS structure to the ASIC electronic circuit;

bonding a service wafer to the semiconductor layer;

flipping the semiconductor layer while bonded to the service wafer, wherein a first one of the steps of forming the MEMS structure and forming the ASIC electronic circuit is performed before flipping the semiconductor layer and a second one of the steps of forming the MEMS structure and forming the ASIC electronic circuit is performed after flipping the semiconductor layer; and

removing a portion of said semiconductor layer, vertically opposite to said first surface, so as to define said second surface and to make said interconnection structures accessible at said second surface, said interconnection structures thereby having a first end at said first surface and a second end at said second surface;

wherein forming said ASIC electronic circuit is performed at said second surface after removing said portion of said semiconductor layer.

12. The process according to claim 11, wherein flipping the semiconductor layer is performed after forming the MEMS structure and before forming the ASIC electronic circuit.

13. A process for manufacturing an integrated semiconductor device, comprising:

forming electrically conductive interconnection structures extending through a silicon semiconductor layer of a silicon-on-insulator (SOI) substrate that also includes a supporting layer and an insulating layer;

forming a micro-electro-mechanical system (MEMS) structure on a first surface of the silicon semiconductor layer, wherein forming the MEMS structure comprises carrying out first processing steps of manufacturing the MEMS structure on the first surface;

bonding a first service wafer over said MEMS structure, and vertically flipping the SOI substrate;

removing the supporting layer and insulating layer after vertically flipping the SOI substrate, thereby exposing a second surface of the silicon semiconductor layer, vertically opposite to the first surface; and

forming an application specific integrated circuit (ASIC) electronic circuit on the second surface of the silicon semiconductor layer, the ASIC electronic circuit being electrically coupled to the MEMS structure by the interconnection structures.

14. The process according to claim 13, wherein bonding the first service wafer over said MEMS structure, and vertically flipping the SOI substrate are performed after carrying out the first processing steps.

15. The process according to claim 13, further comprising, after forming the ASIC electronic circuit, bonding a second service wafer over the ASIC electronic circuit and once again flipping the SOI substrate, wherein forming the MEMS structure further comprises, after once again flipping the SOI substrate:

removing the first service wafer from the first surface; and

carrying out second processing steps of the MEMS structure.

16. The process according to claim 15, wherein the first processing steps comprise forming a sacrificial layer over the first surface and forming an epitaxial layer on the sacrificial layer;

and wherein said second processing steps comprise forming through openings through the epitaxial layer, and carrying out a chemical etch that removes said sacrificial layer and defines at least one suspended element above the silicon semiconductor layer.

17. The process according to claim 15, wherein bonding the second service wafer over the ASIC electronic circuit is performed before once again flipping the SOI substrate.

18. The process according to claim 13, wherein forming the ASIC electronic circuit on the second surface of the silicon semiconductor layer includes forming a complementary metal oxide semiconductor (CMOS) multilayer on the second surface of the silicon semiconductor layer and forming the ASIC electronic circuit in the CMOS multilayer.