Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor

• US 10,202,583 B2
• Filed: 11/21/2017
• Issued: 02/12/2019
• Est. Priority Date: 01/10/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ramaswamy, Durai Vishak Nirmal
• Primary Examiner(s): Tobergte, Nicholas J
• Application Number:
  US15/818,934
• Publication Number:
  US 20180195049A1
• Time in Patent Office: 448 Days
• CPC Class Codes: C12N 15/1133 against herpetoviridae, e.g. HSV
• CPC Class Codes: C12N 2310/113 targeting other non-coding nucleic acids, e.g. antagomirs
• CPC Class Codes: C12N 2310/14 interfering N.A.
• CPC Class Codes: C12N 2310/141 MicroRNAs, miRNAs
• CPC Class Codes: C12N 2310/3231 having an additional ring, e.g. LNA, ENA
• CPC Class Codes: C12N 2710/16211 Lymphocryptovirus, e.g. human herpesvirus 4, Epstein-Barr Virus
• CPC Class Codes: C12N 2710/16263 by chemical treatment
• CPC Class Codes: C12N 7/00 Viruses; Bacteriophages; Compositions thereof; Preparation or purification thereof preparing medicinal viral antigen or antibody compositions, e.g. virus vaccines, A61K39/00
• CPC Class Codes: C12Q 1/701 Specific hybridization probes
• CPC Class Codes: C12Q 1/705 for herpetoviridae, e.g. herpes simplex, varicella zoster
• CPC Class Codes: C12Q 2600/136 Screening for pharmacological compounds
• CPC Class Codes: C12Q 2600/158 Expression markers
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/39 the capacitor and the transistor being in a same trench
• CPC Class Codes: H10B 53/30 : characterised by the memory core region

Abstract

A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.

Claims

1. An array of memory cells individually comprising a capacitor and a vertical transistor, the array comprising rows of word lines and columns of digit lines, comprising:

individual of the columns comprising a digit line under channels of vertical transistors of individual memory cells within the array and interconnecting the transistors in that column;

individual of the rows comprising a word line above the digit lines, the word line extending laterally across and operatively laterally adjacent a lateral side of the transistor channels and interconnecting the transistors in that row; and

capacitors of the individual memory cells within the array individually comprising;

a first capacitor electrode directly against a lateral side of an upper source/drain region of individual of the transistors within the array;

a capacitor insulator over the first capacitor electrode; and

a second capacitor electrode over the capacitor insulator.

2. The array of claim 1 wherein the word line comprises word line pairs extending laterally across a pair of first laterally-opposing sides of the transistor channels in that row.

3. The array of claim 1 wherein the first capacitor electrode is directly against a pair of first laterally-opposing sides of the upper source/drain region of the individual transistors within the array.

4. The array of claim 3 wherein the first capacitor electrode is directly against no more than two laterally-opposing sides of the upper source/drain region of the individual transistors within the array.

5. The array of claim 3 wherein the individual upper source/drain regions have completely encircling peripheral lateral side surfaces, the individual first capacitor electrodes being directly against all of the completely encircling peripheral lateral side surfaces of the individual upper source/drain regions.

6. The array of claim 1 wherein the first capacitor electrodes individually are directly against less than all of the lateral side of the respective upper source/drain region.

7. The array of claim 1 wherein the first capacitor electrodes individually are directly against less than half of the lateral side of the respective upper source/drain region.

8. The array of claim 1 wherein the capacitor insulator comprises programmable material.

9. The array of claim 8 wherein the capacitor insulator comprises programmable ferroelectric material.

10. The array of claim 1 wherein the individual memory cells have a total of only one transistor and a total of only one capacitor.

11. The array of claim 1 wherein the individual memory cells have a total of only two transistors and a total of only two capacitors.

12. An array of memory cells individually comprising a capacitor and a vertical transistor, the array comprising rows of word lines and columns of digit lines, comprising:

individual of the columns comprising a digit line under channels of vertical transistors of individual memory cells within the array and interconnecting the transistors in that column;

individual of the rows comprising a word line above the digit lines, the word line extending laterally across and operatively laterally adjacent a lateral side of the transistor channels and interconnecting the transistors in that row; and

capacitors of the individual memory cells within the array individually comprising;

a first capacitor electrode directly against a pair of first laterally-opposing sides of an upper source/drain region of individual of the transistors within the array;

a capacitor insulator over the first capacitor electrode; and

a second capacitor electrode over the capacitor insulator.

13. The array of claim 12 wherein the individual memory cells have a total of only one transistor and a total of only one capacitor.

14. The array of claim 12 wherein the individual memory cells have a total of only two transistors and a total of only two capacitors.

15. An array of memory cells individually comprising a capacitor and a vertical transistor, the array comprising rows of word lines and columns of digit lines, comprising:

individual of the columns comprising a digit line under channels of vertical transistors of individual memory cells within the array and interconnecting the transistors in that column;

individual of the rows comprising a word line above the digit lines, the word line extending laterally across and operatively laterally adjacent a lateral side of the transistor channels and interconnecting the transistors in that row; and

the individual memory cells comprising a pillar extending elevationally above the digit lines, the pillar comprising one of the transistor channels and an upper source/drain region of individual of the transistors, the pillar having an elevational thickness that is at least three times that of the one transistor channel; and

capacitors of the individual memory cells within the array individually comprising;

a first capacitor electrode directly against a pair of first laterally-opposing sides of the pillar and the upper source/drain region of the respective one individual transistor within the array;

a capacitor insulator over the first capacitor electrode; and

a second capacitor electrode over the capacitor insulator.

16. The array of claim 15 wherein the pillars are formed to be conductive from the upper source/drain regions to tops of the pillars.

17. The array of claim 15 wherein the pillars are formed to be non-conductive from tops of the upper source/drain regions to tops of the pillars.

18. The array of claim 17 wherein the pillars are formed to be insulative from the tops of the upper source/drain regions to the pillar tops.

19. The array of claim 17 wherein the pillars are formed to be semiconductive from the tops of the upper source/drain regions to the pillar tops.

20. The array of claim 15 wherein the first capacitor electrode has a top that is planar and elevationally coincident with a planar top of its pillar.

21. The array of claim 15 wherein the first capacitor electrode has a top that is not elevationally coincident with a top of its pillar.

22. The array of claim 21 wherein the first capacitor electrode top is planar.

23. The array of claim 15 wherein the first capacitor electrode is directly against no more than two laterally-opposing sides of the upper source/drain region of the respective one individual transistors within the array.

24. The array of claim 15 wherein the individual upper source/drain regions have completely encircling peripheral lateral side surfaces, the individual first capacitor electrodes being directly against all of the completely encircling peripheral lateral side surfaces of the individual upper source/drain regions.

25. An array of memory cells individually comprising a capacitor and a vertical transistor, the array comprising rows of word lines and columns of digit lines, comprising:

individual of the columns comprising a digit line under channels of vertical transistors of individual memory cells within the array and interconnecting the transistors in that column;

individual of the rows comprising a word line above the digit lines, the word line extending laterally across and operatively laterally adjacent a lateral side of the transistor channels and interconnecting the transistors in that row; and

capacitors of the individual memory cells within the array individually comprising;

an upwardly-open and downwardly-open first capacitor electrode cylinder completely encircling and directly against all peripheral lateral sides of an upper source/drain region of individual of the transistors within the array;

a capacitor insulator over radially outer sides and radially inner sides of the first capacitor electrode cylinder; and

a second capacitor electrode over the capacitor insulator and over the radially outer sides and the radially inner sides of the first capacitor electrode cylinder.

26. The array of claim 25 wherein the capacitor insulator and the second capacitor electrode are over a majority of the radially internal sides and a majority of the radially external sides of the first capacitor electrode cylinder.

27. The array of claim 25 wherein the capacitor insulator is laterally over all of the radially external sides of the first capacitor electrode cylinder and laterally over only some of the radially internal sides of the first capacitor electrode cylinder.

28. The array of claim 25 wherein the capacitor insulator is directly against tops of the encircled individual upper source/drain regions.

29. The array of claim 25 wherein the capacitor insulator is directly against tops of the first capacitor electrode cylinders.

30. The array of claim 25 wherein the capacitor insulator is directly against tops of the encircled individual upper source/drain regions and is directly against tops of the first capacitor electrode cylinders.

31. A row of memory cells individually comprising a capacitor and a vertical transistor, comprising:

a word line above digit lines, the word line extending laterally across and operatively laterally adjacent a lateral side of channels of vertical transistors of individual memory cells within the row and interconnecting the transistors in the row; and

capacitors of the individual memory cells within the row individually comprising;

a first capacitor electrode directly against a lateral side of an upper source/drain region of individual of the transistors within the row;

a capacitor insulator over the first capacitor electrode; and

a second capacitor electrode over the capacitor insulator.

32. The row of claim 31 wherein the word line comprises word line pairs extending laterally across a pair of first laterally-opposing sides of the transistor channels in the row.

33. The row of claim 31 wherein the first capacitor electrode is directly against a pair of first laterally-opposing sides of the upper source/drain region of the individual transistors within the row.

34. The row of claim 33 wherein the first capacitor electrode is directly against no more than two laterally-opposing sides of the upper source/drain region of the individual transistors within the row.

35. The row of claim 33 wherein the individual upper source/drain regions have completely encircling peripheral lateral side surfaces, the individual first capacitor electrodes being directly against all of the completely encircling peripheral lateral side surfaces of the individual upper source/drain regions.