Phase interpolation circuit

• US 10,203,226 B1
• Filed: 08/11/2017
• Issued: 02/12/2019
• Est. Priority Date: 08/11/2017
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Amiri, Omid Talebi, Tajalli, Armin
• Primary Examiner(s): Timory, Kabir A
• Application Number:
  US15/675,412
• Publication Number:
  US 20190049270A1
• Time in Patent Office: 550 Days
• CPC Class Codes: G01D 5/24404 Interpolation using high frequency signals
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: H03H 11/16 Networks for phase shifting
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Abstract

Methods and systems are described for receiving a control step input at a binary-to-thermometer decoder and responsively generating bits of a thermometer codeword representative of the control step input, providing the bits of the thermometer codeword to a plurality of differential pairs comprising a first transistor and a second transistor, each differential pair configurable for one of directing current to an in-phase (I) common node or directing current to a quadrature phase (Q) common node and switching between directing current to the I common node and the Q common node, and forming an output signal based on current drawn through the I and Q common nodes, the output signal having an intermediate phase with respect to a first and a second reference signal.

Claims

1. An apparatus comprising:

a binary-to-thermometer decoder configured to receive a control step input and to responsively generate a thermometer codeword representative of the control step input;

a plurality of differential pairs configured to generate in-phase (I) and quadrature phase (Q) control signals by drawing respective currents through I and Q common nodes, each differential pair comprising a first transistor and a second transistor connected to a corresponding current source of a plurality of current sources having equal magnitude, each differential pair configured to receive a corresponding bit of the thermometer codeword at an input of the first transistor and a complement of the corresponding bit at an input of the second transistor, the plurality of differential pairs comprising;

a first subset of differential pairs having the first transistor connected to the I common node and the second transistor connected to the Q common node, each differential pair in the first subset configured to control the I and Q control signals; and

a second subset of differential pairs, the second subset of differential pairs comprising (i) differential pairs having the first transistor connected to the I common node and the second transistor disconnected from the Q common node to control only the I control signal and (ii) differential pairs having the first transistor disconnected from the I common node and the second transistor connected to the Q common node to control only the Q control signal; and

a phase interpolator configured to receive (i) first and second reference signals and (ii) the I and Q control signals and to responsively generate an interpolated signal on a differential output node by adding amounts of the first and second reference signals, the amounts of the first and second reference signals determined by magnitudes of the I and Q control signals, respectively.

2. The apparatus of claim 1, wherein the binary-to-thermometer decoder is configured to receive 5 bits and to generate a thermometer codeword having 31 bits.

3. The apparatus of claim 1, further comprising an inverter configured to generate the complements of the bits of the thermometer code.

4. The apparatus of claim 1, wherein a sum of squares of the I and Q control signals is within a threshold of a predetermined constant C.

5. The apparatus of claim 1, wherein the first and second reference signals have a phase difference of 90 degrees.

6. The apparatus of claim 1, wherein the first and second reference signals are sinusoidal signals.

7. The apparatus of claim 1, wherein the first and second reference signals are square wave signals.

8. The apparatus of claim 1, wherein the phase interpolator further comprises respective selection circuits connected to each of the I and Q common nodes, each selection circuit configured to receive a respective reference signal and a corresponding selection bit, the selection circuit configured to determine a polarity of the respective reference signal according to the selection bit.

9. The apparatus of claim 8, wherein each selection circuit comprises two differential pairs of transistors differentially receiving the respective reference signal, each differential pair configured to receive the reference signal in opposite polarity.

10. The apparatus of claim 9, wherein a first differential pair of the two differential pairs is enabled according to the corresponding selection bit and wherein the second differential pair is enabled according to a complement of the corresponding selection bit.

11. A method comprising:

receiving a control step input at a binary-to-thermometer decoder and responsively generating bits of a thermometer codeword representative of the control step input;

providing the bits of the thermometer codeword to a plurality of differential pairs comprising a first transistor and a second transistor connected to a corresponding current source of a plurality of current sources having equal magnitude, each differential pair receiving a corresponding bit of the thermometer codeword at an input of the first transistor and a complement of the corresponding bit at an input of the second transistor;

generating I and Q control signals by drawing respective currents through respective I and Q common nodes via the current sources connected to the plurality of differential pairs, each of the I and Q control signals generated by configuring each differential pair to (i) direct current to only the I common node (ii) to direct current to only the Q common node, or (iii) to switch between directing current to the I common node and the Q common node; and

providing (i) a first and a second reference signal and (ii) the I and Q control signals to a phase interpolator, and responsively forming an output signal on a differential output node by adding amounts of the first and second reference signals, the amounts of the first and the second reference signals determined by magnitudes of the I and Q control signals, respectively, the output signal having an intermediate phase with respect to the first and the second reference signals.

12. The method of claim 11, wherein the control step input comprises 5 bits the thermometer codeword comprises 31 bits.

13. The method of claim 11, wherein the complements of the bits of the thermometer code are generated using an inverter.

14. The method of claim 11, wherein a sum of squares of the I and Q control signals is within a threshold of a predetermined constant C.

15. The method of claim 11, wherein the first and second reference signals have a phase difference of 90 degrees.

16. The method of claim 11, wherein the first and second reference signals are sinusoidal signals.

17. The method of claim 11, wherein the first and second reference signals are square wave signals.

18. The method of claim 11, further comprising determining polarities of the first and second reference signals according to first and second selection bits received at first and second selection circuits, respectively.

19. The method of claim 18, wherein determining the polarity of a given reference signal comprises enabling one transistor of a pair of transistors associated with the corresponding selection circuit, each transistor of the pair receiving the given reference signal in opposite polarity.

20. The method of claim 19, wherein a first transistor of the pair of transistors is enabled according to the selection bit and wherein a second transistor of the pair of transistors is disabled according to a complement of the selection bit.