Memory device including mixed non-volatile memory cell types

• US 10,203,885 B2
• Filed: 01/18/2017
• Issued: 02/12/2019
• Est. Priority Date: 01/18/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Primary Examiner(s): Yang, Han
• Application Number:
  US15/408,671
• Publication Number:
  US 20180203613A1
• Time in Patent Office: 755 Days
• Field of Search: 36518511, 365154
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: H01L 29/516 with at least one ferroelectric layer
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 51/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 51/30 characterised by the memory core region

Abstract

Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.

Claims

1. An apparatus comprising:

a conductive line;

non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other;

an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type, the second memory cell type being different from the first memory cell type; and

a select gate coupled in series with the additional non-volatile memory cell and the non-volatile memory cells, the select gate being between the additional memory cell and the non-volatile memory cells.

2. The apparatus of claim 1, wherein the first memory cell type includes a floating-gate memory cell type.

3. The apparatus of claim 1, wherein the first memory cell type includes a charge-trap memory cell type.

4. The apparatus of claim 1, wherein the second memory cell type includes a ferroelectric memory cell type.

5. The apparatus of claim 1, wherein each of the non-volatile memory cells of the first memory cell type is configured to store more bits of information than the additional non-volatile memory cell.

6. The apparatus of claim 1, wherein the conductive line is part of a data line.

7. An apparatus comprising:

a pillar extending between a conductive material region and a source;

a memory cell string located along the pillar, the memory cell string including memory cells, each of the memory cells including a first structure configured to store information; and

an additional memory cell located along the pillar, the additional memory cell being between the conductive material region and the memory cell string, the additional memory cell including a second structure configured to store information, wherein the first and second structures include different materials.

8. The apparatus of claim 7, further comprising a select gate located along the pillar, the selected gate being between the conductive material region and the memory cell string.

10. The apparatus of claim 7, wherein the second structure includes a ferroelectric material.

11. The apparatus of claim 10, wherein the first structure includes doped polycrystalline silicon.

12. The apparatus of claim 10, wherein the first structure includes silicon nitride.

13. The apparatus of claim 7, where the pillar is located over a semiconductor substrate, and the semiconductor substrate includes circuitry under the pillar.

9. An apparatus comprising:

a pillar extending between a conductive material region and a source;

a memory cell string located along the pillar, the memory cell string including memory cells, each of the memory cells including a first structure configured to store information;

an additional memory cell located along the pillar, the additional memory cell being between the conductive material region and the memory cell string, the additional memory cell including a second structure configured to store information, wherein the first and second structures include different materials; and

a select gate located along the pillar, the selected gate being between the conductive material region and the memory cell string, wherein the select gate is between the additional memory cell and the memory cell string.