Data writing method, memory control circuit unit and memory storage apparatus for writing data from buffer memory and moving valid data

• US 10,203,886 B2
• Filed: 03/24/2016
• Issued: 02/12/2019
• Est. Priority Date: 02/05/2016
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Huang, Jia-Yan
• Primary Examiner(s): Bragdon, Reginald G
• Assistant Examiner(s): Westbrook, Michael L
• Application Number:
  US15/080,557
• Publication Number:
  US 20170228171A1
• Time in Patent Office: 1,055 Days
• Field of Search: None
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A data writing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: determining whether receiving a predetermined command from a host system. The method also includes: if receiving the predetermined command from the host system, writing at least one buffer data from a buffer memory into a first physical erasing unit, selecting at least one second physical erasing unit from the physical erasing units, and writing at least one valid data of the at least one second physical erasing unit into the first physical erasing unit in response to the predetermined command.

Claims

1. A data writing method for a rewritable non-volatile memory module of a memory storage apparatus, wherein the memory storage apparatus has a buffer memory, the rewritable non-volatile memory module has a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical programming units, the data writing method comprising:

determining whether a predetermined command is received from a host system;

if the predetermined command is received from the host system, writing at least one buffer data from the buffer memory into a first physical erasing unit among the physical erasing units, selecting at least one second physical erasing unit from the physical erasing units, and writing at least one valid data of the at least one second physical erasing unit into the first physical erasing unit;

determining whether a quantity of the at least one buffer data is less than a predetermined threshold;

if the quantity of the at least one buffer data is less than the predetermined threshold, writing at least one dummy data into the first physical erasing unit; and

only if the quantity of the at least one buffer data is not less than the predetermined threshold, performing the step of selecting the at least one second physical erasing unit from the physical erasing units and writing the at least one valid data of the at least one second physical erasing unit into the first physical erasing unit,

wherein a number of bits stored in each first memory cell of the at least one first physical erasing unit equals to a number of bits stored in each second memory cell of the at least one second physical erasing unit.

2. The data writing method according to claim 1, wherein the step of writing the at least one valid data of the at least one second physical erasing unit into the first physical erasing unit comprises:

filling available storage spaces of the first physical erasing unit with the at least one valid data.

3. The data writing method according to claim 1, wherein the predetermined command is a flush command or a suspend command.

4. The data writing method according to claim 1, further comprising:

performing an erasing operation on the at least one second physical erasing unit.

5. The data writing method according to claim 1, wherein the plurality of physical programming units comprise a plurality of lower physical programming units, a plurality of center physical programming units and a plurality of upper physical programming units.

6. A memory control circuit unit for controlling a rewritable non-volatile memory module, the memory control circuit unit comprising:

a host interface configured to be coupled to a host system;

a memory interface configured to be coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical programming units;

a buffer memory coupled to the host interface and the memory interface and configured to store at least one buffer data; and

a memory management circuit coupled to the host interface, the memory interface and the buffer memory and configured to determine whether a predetermined command is received from the host system,

wherein if the predetermined command is received from the host system, the memory management circuit is further configured to issue a first command sequence to write the at least one buffer data from the buffer memory into a first physical erasing unit among the physical erasing units, select at least one second physical erasing unit from the physical erasing units, and issue a second command sequence to write at least one valid data of the at least one second physical erasing unit into the first physical erasing unit,

wherein the memory management circuit is further configured to determine whether a quantity of the at least one buffer data is less than a predetermined threshold,

if the quantity of the at least one buffer data is less than the predetermined threshold, the memory management circuit is further configured to issue a third command sequence to write at least one dummy data into the first physical erasing unit,

only if the quantity of the at least one buffer data is not less than the predetermined threshold, the memory management circuit is configured to perform the operation of selecting the at least one second physical erasing unit from the physical erasing units and issuing the second command sequence to write the at least one valid data of the at least one second physical erasing unit into the first physical erasing unit,

wherein a number of bits stored in each first memory cell of the at least one first physical erasing unit equals to a number of bits stored in each second memory cell of the at least one second physical erasing unit.

7. The memory control circuit unit according to claim 6, wherein in the operation of writing the at least one valid data of the at least one second physical erasing unit into the first physical erasing unit, the memory management circuit fills available storage spaces of the first physical erasing unit with the at least one valid data.

8. The memory control circuit unit according to claim 6, wherein the predetermined command is a flush command or a suspend command.

9. The memory control circuit unit according to claim 6, wherein the memory management circuit is further configured to issue a fourth command sequence to perform an erasing operation on the at least one second physical erasing unit.

10. The memory control circuit unit according to claim 6, wherein the plurality of physical programming units comprise a plurality of lower physical programming units, a plurality of center physical programming units and a plurality of upper physical programming units.

11. A memory storage apparatus, comprising:

a connection interface unit configured to be coupled to a host system;

a rewritable non-volatile memory module having a plurality of physical erasing units, wherein each of the physical erasing units has a plurality of physical programming units; and

a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module and comprising a buffer memory, wherein the buffer memory is configured to store at least one buffer data,

wherein the memory control circuit unit is configured to determine whether a predetermined command is received from the host system,

wherein if the predetermined command is received from the host system, the memory control circuit unit is further configured to issue a first command sequence to write the at least one buffer data from the buffer memory into a first physical erasing unit among the physical erasing units, select at least one second physical erasing unit from the physical erasing units, and issue a second command sequence to write at least one valid data of the at least one second physical erasing unit into the first physical erasing unit,

wherein the memory control circuit unit is further configured to determine whether a quantity of the at least one buffer data is less than a predetermined threshold,

if the quantity of the at least one buffer data is less than the predetermined threshold, the memory control circuit unit is further configured to issue a third command sequence to write at least one dummy data into the first physical erasing unit,

only if the quantity of the at least one buffer data is not less than the predetermined threshold, the memory control circuit unit is configured to perform the operation of selecting the at least one second physical erasing unit from the physical erasing units and issuing the second command sequence to write the at least one valid data of the at least one second physical erasing unit into the first physical erasing unit,

wherein a number of bits stored in each first memory cell of the at least one first physical erasing unit equals to a number of bits stored in each second memory cell of the at least one second physical erasing unit.

12. The memory storage apparatus according to claim 11, wherein in the operation of writing the at least one valid data of the at least one second physical erasing unit into the first physical erasing unit, the memory control circuit unit fills available storage spaces of the first physical erasing unit with the at least one valid data.

13. The memory storage apparatus according to claim 11, wherein the predetermined command is a flush command or a suspend command.

14. The memory storage apparatus according to claim 11, wherein the memory control circuit unit is further configured to issue a fourth command sequence to perform an erasing operation on the at least one second physical erasing unit.

15. The memory storage apparatus according to claim 11, wherein the plurality of physical programming units comprise a plurality of lower physical programming units, a plurality of center physical programming units and a plurality of upper physical programming units.