Systems and methods for side data based soft data flash memory access

• US 10,204,006 B2
• Filed: 10/28/2015
• Issued: 02/12/2019
• Est. Priority Date: 10/28/2015
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Inventors: Zhao, Zhijun, Yang, Shaohua
• Primary Examiner(s): Chung, Phung M
• Application Number:
  US14/925,755
• Publication Number:
  US 20170123901A1
• Time in Patent Office: 1,203 Days
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/6577 Representation or format of variables, register sizes or word-lengths and quantization
• CPC Class Codes: H03M 13/6588 Compression or short representation of variables

Abstract

Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.

Claims

1. A method, comprising:

accessing a first set of memory cells having a series of voltages written to the first set of memory cells, each cell having a voltage value representing codewords stored to the cell;

receiving the voltage value of the each cell;

comparing the voltage value of the each cell to a first threshold to determine a first binary set of the each cell, the first binary set including a first group of binary values;

comparing the voltage value of the each cell to a second threshold to determine a second binary set of the each cell, the second binary set including a second group of binary values and a third group of binary values;

generating a soft data representation of the codewords using a combination of the second group of binary values and at least one side data value;

decoding the soft data representation to obtain recovered read data; and

storing the recovered read data.

2. The method of claim 1, further comprising applying a low density parity check encoding algorithm to a user data set to yield the codewords.

3. The method of claim 1, further comprising applying a second encoding algorithm to a combination of the codewords to yield the voltage values.

4. The method of claim 1, wherein the soft data representation comprises a first set of soft data values, a second set of soft data values, and a third set of soft data values, each generated by combining a respective one of the second group of binary values and a corresponding element of the side data values.

5. The method of claim 4, wherein the first set of soft data values corresponds to a first low density parity check codeword, the second set of soft data values corresponds to a second low density parity check codeword, and the third set of soft data values corresponds to a third low density parity check codeword.

6. The method of claim 4, further comprising generating the at least one side data value by resolving the first set of soft data values to yield corresponding hard data values.

7. The method of claim 4, wherein the side data set corresponds to at least one of the first group of binary values, the second group of binary values, and the third group of binary values.

8. The method of claim 7, further comprising comparing the voltage value of the each cell to a third threshold to determine a third binary set of the each cell.

9. The method of claim 8, further comprising generating, by using the first data decoding circuit, a fourth set of soft data values each corresponding to a combination of a respective one of the third group of binary values and a corresponding element of the side data values and a fifth set of soft data values each corresponding to a combination of a respective one of the third group of binary values and a corresponding element of the side data values.

10. The method of claim 4, further comprising decoding, by a second data decoding circuit, the first set of soft data values to yield a first decoded output, the second set of soft data values to yield a second decoded output, and the third set of soft data values to yield a third decoded output.

11. A system, comprising:

a first set of memory cells having a series of voltages written to the first set of memory cells, wherein each cell has a voltage value representing codewords stored to the cell;

a data read circuit operable to;

compare the voltage value of the each cell to a first threshold to determine a first binary set of the each cell, the first binary set including a first group of binary values;

compare the voltage value of the each cell to a second threshold to determine a second binary set of the each cell, the second binary set including a second group of binary values and a third group of binary values;

a storage buffer operable to store side data values;

a first data decoding circuit operable to generate a soft data representation of the codewords using a combination of the second group of binary values and at least some of the side data values; and

a second data decoding circuit operable to decode the soft data representation to obtain recovered read data.

12. The system of claim 11, wherein a low density parity check encoding algorithm is applied to a user data set to yield the codewords.

13. The system of claim 11, wherein a second encoding algorithm is applied to a combination of the codewords to yield the voltage values.

14. The system of claim 11, wherein the soft data representation comprises a first set of soft data values, a second set of soft data values, and a third set of soft data values, each generated by combining a respective one of the second group of binary values and a corresponding element of the side data values.

15. The system of claim 14, wherein the first set of soft data values corresponds to a first low density parity check codeword, the second set of soft data values corresponds to a second low density parity check codeword, and the third set of soft data values corresponds to a third low density parity check codeword.

16. The system of claim 14, further comprising generating the side data values by resolving the first set of soft data values to yield corresponding hard data values.

17. The system of claim 14, wherein the first data decoding circuit generates the first set of soft data values, the second set of soft data values, and the third set of soft data values.

18. The system of claim 17, further comprising comparing the voltage value of the each cell to a third threshold to determine a third binary set of the each cell.

19. The system of claim 18, further comprising generating, by using the first data decoding circuit, a fourth set of soft data values each corresponding to a combination of a respective one of the third group of binary values and a corresponding element of the side data values and a fifth set of soft data values each corresponding to a combination of a respective one of the third group of binary values and a corresponding element of the side data values.

20. The system of claim 14, wherein the second data decoding circuit decodes the first set of soft data values to yield a first decoded output, the second set of soft data values to yield a second decoded output, and the third set of soft data values to yield a third decoded output.