Systems and methods for inter-cell interference mitigation in a flash memory

• US 10,204,007 B2
• Filed: 01/12/2016
• Issued: 02/12/2019
• Est. Priority Date: 05/22/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Zhang, Fan, Li, Shu, Xiao, Jun, Xia, Haitao
• Primary Examiner(s): Abraham, Esaw T
• Application Number:
  US14/994,001
• Publication Number:
  US 20160124808A1
• Time in Patent Office: 1,127 Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/00 Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C

Abstract

The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory. The systems and methods may include a soft information correction circuit that is operable to receive soft information corresponding to information accessed from a block of memory cells, and modify the soft information based upon a variance of the soft information and a median of the soft information to create corrected soft information, the corrected soft information being used to mitigate inter-cell interference in the block of memory cells.

Claims

1. A data processing system, the data processing system comprising:

a soft information correction circuit operable to;

access a series of bit patterns from a block of memory cells;

generate soft information corresponding to the series of bit patterns accessed from the block of memory cells, the soft information comprising a probability that voltage levels indicated by the series of bit patterns are correct;

calculate an offset reduced output based upon a combination of a variance of the soft information and a median of the soft information;

modify the soft information based at least in part on the offset reduced output to create corrected soft information; and

mitigate inter-cell interference in the block of memory cells using the corrected soft information.

2. The data processing system of claim 1, wherein the data processing system further comprises:

a data decoder circuit operable to decode the corrected soft information to yield a data output.

3. The data processing system of claim 2, wherein the data decoder circuit is a low density data decoder circuit.

4. The data processing system of claim 1, wherein the variance includes a left side variance and a right side variance, the soft information correction circuit is further operable to calculate an offset reduced output based upon a combination of the right side variance, the left side variance, and the median, and modifying the corrected soft information is further based at least in part upon the offset reduced output.

5. The data processing system of claim 1, wherein the soft information comprises log likelihood information.

6. The data processing system of claim 1, wherein the data processing system is implemented as an integrated circuit.

7. The data processing system of claim 1, wherein the data processing system is incorporated in a storage device, the storage device comprising:

a block of flash memory cells, wherein the block of memory cells are a subset of the block of flash memory cells.

8. The data processing system of claim 7, wherein each of the flash memory cells are multi-bit memory cells.

9. The data processing system of claim 8, wherein the multi-bit memory cells are each capable of storing a voltage level representative of a number of bits, and wherein the number of bits is selected from a group consisting of:

two bits, and three bits.

10. A method for accessing information from a storage device, the method comprising:

accessing a series of bit patterns from a block of memory cells;

generating soft information corresponding to the series of bit patterns accessed from the block of memory cells, the soft information comprising a probability that voltage levels indicated by the series of bit patterns are correct;

calculating an offset reduced output based upon a combination of a variance of the soft information and a median of the soft information;

modifying the soft information based at least in part on the offset reduced output to create corrected soft information; and

mitigating inter-cell interference in the block of memory cells using the corrected soft information.

11. The method of claim 10, wherein decoding the corrected soft information is based at least in part on a low density parity check decoding algorithm.

12. The method of claim 10, wherein the variance includes a left side variance and a right side variance, the method further comprising:

calculating an offset reduced output based upon a combination of the right side variance, the left side variance, and the median; and

modifying the soft information is based at least in part upon the offset reduced output.

13. The method of claim 10, wherein the soft information comprises log likelihood information.

14. A storage device, the storage device comprising:

a block of memory cells;

a soft information correction circuit operable to;

access a series of bit patterns from a block of memory cells;

receive soft information corresponding to the series of bit patterns accessed from the block of memory cells, the soft information comprising a probability that voltage levels indicated by the series of bit patterns are correct;

calculate an offset reduced output based upon a combination of a variance of the soft information and a median of the soft information;

modify the soft information based at least in part on the offset reduced output to create corrected soft information; and

mitigate inter-cell interference in the block of memory cells using the corrected soft information.

15. The storage device of claim 14, wherein each of the memory cells is operable to store a voltage level representing two or more bits.