Memory-side caching for shared memory objects

• US 10,204,050 B2
• Filed: 04/24/2017
• Issued: 02/12/2019
• Est. Priority Date: 04/24/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Katayama, Yasunao
• Primary Examiner(s): Farrokh, Hashem
• Application Number:
  US15/495,145
• Publication Number:
  US 20180307604A1
• Time in Patent Office: 659 Days
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

Methods and systems for memory-side shared caching include determining whether a requested memory access is directed to shared portion of memory by referencing a lock address list in a memory controller. If the requested memory access is for the shared portion of memory, it is determined whether an associated data object is present in a memory-side cache. If the associated data object is present in the memory-side cache, the memory-side cache is accessed. If the associated data object is not present in the memory-side cache, an external memory is accessed.

Claims

1. A method for memory-side shared caching, comprising:

determining whether a requested memory access is directed to shared portion of memory by referencing a lock address list in a memory controller;

if the requested memory access is for the shared portion of memory, determining whether an associated data object is present in a memory-side cache;

if the associated data object is present in the memory-side cache, accessing the memory-side cache; and

if the associated data object is not present in the memory-side cache, accessing an external memory.

2. The method of claim 1, further comprising performing a cache replacement with the associated data object if the associated data object is not present in the memory-side cache to enter the requested data object in the memory-side cache.

3. The method of claim 2, further comprising recording an address for the requested data object in a memory-side cache tag entry.

4. The method of claim 3, further comprising setting a “

valid”

control bit in a memory-side cache tag to indicate that an entry in the memory-side cache stores a valid data object.

5. The method of claim 3, further comprising setting a “

consume”

control bit in a memory-side cache tag for the associated data object to indicate whether a paired access to the associated data object has completed.

6. The method of claim 1, further comprising accessing the associated data object from a memory outside the memory controller if the requested memory access is not directed to shared portion of memory.

7. A non-transitory computer readable storage medium comprising a computer readable program for memory-side caching, wherein the computer readable program when executed on a computer causes the computer to perform the steps of claim 1.

8. A memory controller, comprising:

an input/output (I/O) interface configured to communicate with one or more external processing elements and an external memory;

a memory-side cache configured to store shared data objects;

a lock address list; and

a cache operation module configured to determine whether a requested memory access is directed to a shared portion of memory by referencing the lock address list, to determine whether an associated data object is present in the memory-side cache if the requested memory access is for the shared portion of memory, to access the memory-side cache if the associated data object is present in the memory-side cache, and to access the external memory if the associated data object is not present in the memory-side cache.

9. The memory controller of claim 8, wherein the cache operation module is further configured to perform a cache replacement with the associated data object if the associated data object is not present in the memory-side cache to enter the requested data object in the memory-side cache.

10. The memory controller of claim 9, wherein the cache operation module is further configured to record an address for the requested data object in a memory-side cache tag entry.

11. The memory controller of claim 10, wherein the cache operation module is further configured to set a “

valid”

control bit in a memory-side cache tag to indicate that an entry in the memory-side cache stores a valid data object.

12. The memory controller of claim 8, wherein the cache operation module is further configured to set a “

consume”

control bit in a memory-side cache tag for the associated data object to indicate whether a paired access to the associated data object has completed.

13. The memory controller of claim 8, wherein the cache operation module is further configured to access the associated data object from the memory outside the memory controller if the requested memory access is not directed to shared portion of memory.

14. A processing system, comprising:

one or more processing elements;

a main memory; and

a memory controller in communication with the one or more processing elements and the main memory, the memory controller comprising;

a memory-side cache configured to store shared data objects;

a lock address list; and

a cache operation module configured to determine whether a requested memory access is directed to a shared portion of memory by referencing the lock address list, to determine whether an associated data object is present in the memory-side cache if the requested memory access is for the shared portion of memory, to access the memory-side cache if the associated data object is present in the memory-side cache, and to access the main memory if the associated data object is not present in the memory-side cache.

15. The processing system of claim 14, wherein the cache operation module is further configured to perform a cache replacement with the requested data object if the requested data object is not present in the memory-side cache to enter the requested data object in the memory-side cache.

16. The processing system of claim 15, wherein the cache operation module is further configured to set a “

valid”

control bit to indicate that an entry in the memory-side cache stores a valid data object.

17. The processing system of claim 14, wherein the cache operation module is further configured to set a “

consume”

control bit for the requested data object to indicate whether a paired access to the requested data object has completed.

18. The processing system of claim 14, wherein the cache operation module is further configured to access the associated data object from main memory if the requested memory access is not directed to a shared portion of memory.

19. The processing system of claim 14, wherein the one or more processing elements each comprise a processor-side cache configured to store non-shared data objects.