Input buffer circuit

• US 10,204,666 B2
• Filed: 02/09/2018
• Issued: 02/12/2019
• Est. Priority Date: 02/14/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tsukada, Shuichi
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/893,398
• Publication Number:
  US 20180233180A1
• Time in Patent Office: 368 Days
• Field of Search: 36518905, 365226, 365205
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.

Claims

1. An apparatus comprising:

a first voltage switch configured to provide a first power supply voltage from a first power terminal responsive to a clock signal;

a first amplifier configured to receive a first input voltage and a second input voltage, and further configured to provide a first intermediate voltage on a first node and a second intermediate voltage on a second node, responsive to the first power supply voltage provided by the first voltage switch;

a second voltage switch configured to provide a second power supply voltage from a second power terminal responsive to one of the first intermediate voltage and the second intermediate voltage; and

a second amplifier configured to provide one of a first output voltage and a second output voltage responsive to the second power supply voltage from the second voltage switch,

wherein the second amplifier is configured to be activated via the second voltage switch by one of a first precharge voltage from a third node responsive to the first intermediate voltage of the first node. and a second precharge voltage from the third node responsive to the second intermediate voltage of the second node.

2. The apparatus of claim 1, wherein the first power supply voltage has a same voltage level as the second power supply voltage.

3. The apparatus of claim 1, wherein the first input voltage is provided as a data input signal and the second input voltage is provided as a reference voltage.

4. An apparatus comprising:

a first voltage switch configured to provide a first power supply voltage from a first power terminal responsive to a clock signal;

a first amplifier configured to receive a first input voltage and a second input voltage, and further configured to provide a first intermediate voltage on a first node and a second intermediate voltage on a second node. responsive to the first power supply voltage provided by the first voltage switch;

a second voltage switch configured to provide a second power supply voltage from a second power terminal responsive to one of the first intermediate voltage and the second intermediate voltage;

a second amplifier configured to provide one of a first output voltage and a second output voltage responsive to the second power supply voltage from the second voltage switch; and

a first transistor coupled between the first node and a fourth node, and a second transistor coupled between the second node and a fifth node,

wherein the second amplifier is configured to provide the one of the first output voltage to the fourth node, and the second output voltage to the fifth node.

5. The apparatus of claim 4, wherein the second amplifier is configured to be activated when one of a voltage level of the first node exceeds a first threshold voltage of the first transistor, and a voltage level of the second node exceeds a second threshold voltage of the second transistor.

6. The apparatus of claim 4, wherein the second amplifier is configured to be activated when the first intermediate voltage exceeds a first threshold voltage of the first transistor, or the second intermediate voltage exceeds a second threshold voltage of the second transistor.

7. An apparatus comprising:

a first voltage switch configured to provide a first power supply voltage from a first power terminal responsive to a clock signal;

a first amplifier configured to receive a first input voltage and a second input voltage, and further configured to provide a first intermediate voltage on a first node and a second intermediate voltage on a second node. responsive to the first power supply voltage provided by the first voltage switch;

a second voltage switch configured to provide a second power supply voltage from a second power terminal responsive to one of the first intermediate voltage and the second intermediate voltage;

a second amplifier configured to provide one of a first output voltage and a second output voltage responsive to the second power supply voltage from the second voltage switch; and

a third transistor configured to provide a first precharge voltage from a first precharge terminal to a gate of the second voltage switch, and a fourth transistor configured to provide a second precharge voltage from a second precharge terminal to the gate of the second voltage switch.

8. The apparatus of claim 7, wherein a gate of the third transistor is configured to be turned on responsive to the first intermediate voltage, and

wherein a gate of the fourth transistor is configured to be turned on responsive to the second intermediate voltage.

9. The apparatus of claim 7, wherein the second amplifier further includes:

a first inverter coupled between the second voltage switch and a third precharge terminal; and

a second inverter coupled between the second voltage switch and a fourth precharge terminal.

10. An apparatus comprising:

a first voltage switch configured to provide a first power supply voltage from a first power terminal responsive to a clock signal;

a first amplifier configured to be activated by the first power supply voltage, and further configured to receive a first input voltage and a second input voltage and provide a first intermediate voltage on a first node and a second intermediate voltage on a second node;

a second voltage switch coupled to a third node and configured to provide a second power supply voltage from a second power terminal responsive to one of the first intermediate voltage and the second intermediate voltage;

a first transistor coupled between the first node and a fourth node and a second transistor coupled between the second node and a fifth node; and

a second amplifier configured to provide one of a first output voltage and a second output voltage to the fourth node and the fifth node, respectively, responsive to the second power supply voltage received from the second voltage switch.

11. The apparatus of claim 10, wherein the first power supply voltage has a same voltage level as the second power supply voltage.

12. The apparatus of claim 10, wherein the first input voltage is provided as a data input signal and the second input voltage is provided as a reference voltage.

13. The apparatus of claim 10, wherein the first output voltage provided to the fourth node is increased when the first intermediate voltage of the first node exceeds a first threshold voltage of the first transistor, and

wherein the second output voltage provided to the fifth node is increased when the second intermediate voltage on the second node exceeds a second threshold voltage of the second transistor.

14. The apparatus of claim 10, further comprising

a third transistor configured to provide a first precharge voltage from a first precharge terminal to the third node;

and

a fourth transistor configured to provide a second precharge voltage from a second precharge terminal to the third node,

wherein a gate of the third transistor is configured to be turned on responsive to the first intermediate voltage, and

wherein a gate of the fourth transistor is configured to be turned on responsive to the second intermediate voltage.

15. The apparatus of claim 10, wherein the second amplifier is activated when one of the first intermediate voltage of the first node exceeds a first threshold voltage of the first transistor and the second intermediate voltage of the second node exceeds a second threshold voltage of the second transistor.