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Semiconductor device with first and second chips and connections thereof and a manufacturing method of the same

  • US 10,204,899 B2
  • Filed: 09/11/2017
  • Issued: 02/12/2019
  • Est. Priority Date: 07/30/2004
  • Status: Active Grant
First Claim
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1. A semiconductor device including a DC-DC converter, comprising:

  • first and second die pads;

    a lead arranged near the second die pad than the first die pad;

    a first semiconductor chip formed over the first die pad and electrically connected with the first die pad;

    a second semiconductor chip formed over the second die pad and electrically connected with the second die pad; and

    a driver chip configured to control the first and second semiconductor chips,wherein the first semiconductor chip includes a first MOSFET having a first gate electrode, a first source and a first drain,wherein the second semiconductor chip includes a schottky barrier diode and a plurality of power MOSFETs which are formed on a semiconductor substrate,wherein the semiconductor substrate includes a first long side, a second long side located on the opposite side of the first long side, a first short side and a second short side located on the opposite side of the first short side,wherein the schottky barrier diode is formed in a first region of the semiconductor substrate and includes an anode electrode and a cathode electrode,wherein the plurality of power MOSFETs are formed in a plurality of second regions of the semiconductor substrate and respectively include a second gate electrode, a second source and a second drain,wherein a first gate metal electrically connected with the first gate electrode and a first source metal electrically connected with the first source are formed over a top surface of the first semiconductor chip,wherein a first drain electrode electrically connected with the first drain is formed over a rear surface of the first semiconductor chip,wherein a second gate metal is formed over the semiconductor substrate, is electrically connected to the second gate electrodes and surrounds the first region and the second regions in a planar view,wherein a plurality of gate fingers are unified with the first metal layer, are extending to a direction along the first short side and are arranged between each of the second regions,wherein a second source metal is formed over the first region and the second regions and is electrically connected to the second sources and the anode electrode,wherein a second drain electrode electrically connected with the second drains is formed over a rear surface of the second semiconductor chip,wherein the driver chip includes a first electrode pad and a second electrode pad,wherein the first electrode pad and the first gate metal are electrically connected by a first wire,wherein the second electrode pad and the second gate metal are electrically connected by a second wire,wherein the first source metal and the second die pad are electrically connected by a first metal sheet,wherein the second source metal and the lead are electrically connected by a second metal sheet, andwherein a length along the first long side of the first region is larger than a length along the first short side of the first region.

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