Making electrical components in handle wafers of integrated circuit packages

• US 10,204,977 B2
• Filed: 11/06/2017
• Issued: 02/12/2019
• Est. Priority Date: 05/02/2014
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Wang, Liang, Shen, Hong, Katkar, Rajesh
• Primary Examiner(s): Smith, Bradley K
• Application Number:
  US15/804,847
• Publication Number:
  US 20180076278A1
• Time in Patent Office: 463 Days
• Field of Search: None
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/11 the devices being of a type provided for in group H01L29/00
• CPC Class Codes: H01L 25/115 the devices being arranged next to each other
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 : Electrodes
• CPC Class Codes: H01L 28/65 : comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1205 : Capacitor
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16153 : Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]

Abstract

Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure'"'"'s cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.

Claims

1. A fabrication method comprising:

(a) obtaining a first integrated circuit structure comprising a first substrate comprising a bottom surface having a cavity, and comprising a first circuitry comprising one or more first capacitors each of which is at least partially located in a respective first hole formed in a top surface of the first substrate, each first capacitor comprising;

a first electroconductive layer formed within or upon an interior surface of the respective first hole;

a dielectric layer formed over the first electroconductive layer and at least partially located in the respective first hole;

a second electroconductive layer formed over the dielectric layer and at least partially located in the respective first hole;

(b) obtaining a second integrated circuit structure comprising a second substrate comprising a second circuitry comprising one or more second capacitors each of which is at least partially located in a respective second hole formed in a top surface of the second substrate, each second capacitor comprising;

a first electroconductive layer formed within or upon an interior surface of the respective second hole;

a dielectric layer formed over the first electroconductive layer and at least partially located in the respective second hole;

a second electroconductive layer formed over the dielectric layer and at least partially located in the respective second hole;

the second integrated circuit structure further comprising a semiconductor die attached to the top surface of the second substrate and electroconductively coupled to the second circuitry;

(c) after obtaining the first and second integrated circuit structures, positioning the first and second integrated circuit structures to align each first hole with a corresponding second hole, and bonding the first integrated structure to the second integrated structure, the bonding comprising bonding the first substrate to the second substrate, wherein in said bonding of the first and second integrated structures, for each aligned pair of a first hole and a second hole, the first electroconductive layer of the respective first capacitor becomes electroconductively coupled to the second electroconductive layer of the respective second capacitor;

wherein at a conclusion of said bonding of the first and second integrated circuit structures, the semiconductor die is disposed in the cavity but is spaced from the first substrate to define a headspace between the cavity surface and the semiconductor die surface;

wherein the method further comprises injecting a filler into the headspace through one or more channels in the first substrate that communicate between the cavity and the top surface of the first substrate.

2. The method of claim 1 wherein for at least one aligned pair of a first hole and a second hole, at least one of the first and second structures comprises an electroconductive pad positioned, at a conclusion of said bonding, between the first electroconductive layer of the respective first capacitor and the second electroconductive layer of the respective second capacitor and electroconductively coupling the first electroconductive layer of the respective first capacitor to the second electroconductive layer of the respective second capacitor.

3. The method of claim 2 wherein at least one said electroconductive pad is part of the first structure.

4. The method of claim 3 wherein for at least one said electroconductive pad which is part of the first structure, the respective first hole is a through silicon via.

5. The method of claim 4 wherein an entire portion of the through silicon via over the dielectric layer of the respective first capacitor is filled by the second electroconductive layer of the respective first capacitor.

6. The method of claim 2 wherein at least one said electroconductive pad is part of the second structure.

7. The method of claim 1 wherein for at least one aligned pair of a first hole and a second hole, each of the first and second structures comprises an electroconductive pad positioned, at a conclusion of said bonding, between the first electroconductive layer of the respective first capacitor and the second electroconductive layer of the respective second capacitor, the electroconductive pads being bonded to each other and electroconductively coupling the first electroconductive layer of the respective first capacitor to the second electroconductive layer of the respective second capacitor.

8. The method of claim 1 wherein the second electroconductive layer of at least one first capacitor fills an entire portion of the respective first hole over the respective dielectric layer.

9. The method of claim 1 wherein the second electroconductive layer of at least one second capacitor fills the respective second hole over the respective dielectric layer.

10. The method of claim 1 wherein in at least one first capacitor, the first electroconductive layer comprises an electroconductive layer formed over a surface of the respective first hole.

11. The method of claim 1 wherein in at least one first capacitor, the first electroconductive layer comprises a doped semiconductor layer formed in the surface of the respective first hole.

12. The method of claim 1 wherein in at least one second capacitor, the first electroconductive layer comprises an electroconductive layer formed over a surface of the respective second hole.

13. The method of claim 1 wherein in at least one second capacitor, the first electroconductive layer comprises a doped semiconductor layer formed in the surface of the respective second hole.

14. The method of claim 1 wherein the filler is epoxy.

15. An integrated circuit package comprising:

(a) a first integrated circuit structure comprising a first substrate comprising a bottom surface having a cavity, and comprising a first circuitry comprising one or more first capacitors each of which is at least partially located in a respective first hole formed in a top surface of the first substrate, each first capacitor comprising;

a first electroconductive layer comprising at least one of;

(i) an electroconductive layer formed over a surface of the respective first hole;

(ii) a doped semiconductor layer formed in the surface of the respective first hole;

a dielectric layer formed over the first electroconductive layer and at least partially located in the respective first hole;

a second electroconductive layer formed over the dielectric layer and at least partially located in the respective first hole;

(b) a second integrated circuit structure comprising a second substrate comprising a second circuitry comprising one or more second capacitors each of which is at least partially located in a respective second hole formed in a top surface of the second substrate, each second capacitor comprising;

a first electroconductive layer comprising at least one of;

(i) an electroconductive layer formed over a surface of the respective second hole;

(ii) a doped semiconductor layer formed in the surface of the respective second hole;

a dielectric layer formed over the first electroconductive layer and at least partially located in the respective second hole;

a second electroconductive layer formed over the dielectric layer and at least partially located in the respective second hole;

wherein the first substrate is bonded to the second substrate, each first hole being aligned with a corresponding second hole, wherein for each aligned pair of a first hole and a second hole, the first electroconductive layer of the first capacitor is electroconductively coupled to the second electroconductive layer of the respective second capacitor;

wherein the semiconductor die is disposed in the cavity but is spaced from the first substrate to define a headspace between the cavity surface and the semiconductor die surface, the headspace being filled with a filler;

wherein the first substrate comprises one or more channels communicating between the cavity and the top surface of the first substrate and suitable for injecting a material into the cavity to form the filler.

16. The integrated circuit package of claim 15 wherein for at least one pair of a first hole and the corresponding second hole, at least one of the first and second structures comprises an electroconductive pad located between the first electroconductive layer of the respective first capacitor and the second electroconductive layer of the respective second capacitor and electroconductively coupling the first electroconductive layer of the respective first capacitor to the second electroconductive layer of the respective second capacitor.

17. The integrated circuit package of claim 16 wherein at least one said electroconductive pad is part of the first structure.

18. The integrated circuit package of claim 17 wherein for at least one said electroconductive pad which is part of the first structure, the respective first hole is a through silicon via.

19. The integrated circuit package of claim 18 wherein an entire portion of the through silicon via over the dielectric layer of the respective first capacitor is filled by the second electroconductive layer of the respective first capacitor.

20. The integrated circuit package of claim 15 wherein the filler is epoxy.