Bottom source NMOS triggered Zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)

• US 10,205,017 B2
• Filed: 09/25/2013
• Issued: 02/12/2019
• Est. Priority Date: 06/17/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur
• Primary Examiner(s): Chen, Yu
• Assistant Examiner(s): Vu, Pauline
• Application Number:
  US14/037,205
• Publication Number:
  US 20150084117A1
• Time in Patent Office: 1,966 Days
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0716 in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 29/66234 Bipolar junction transistors [BJT]
• CPC Class Codes: H01L 29/6628 Inverse transistors
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/70 Bipolar devices
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7327 Inverse vertical transistors
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.

Claims

1. A method of forming a transient voltage suppressing (TVS) device comprising:

forming an epitaxial layer of a first conductivity type on top of a semiconductor substrate wherein the semiconductor substrate comprises a heavily doped bottom layer of the first conductivity type;

forming a trench gate padded with a gate insulation layer and filled with a gate material in the trench gate in the epitaxial layer;

forming a body region with a second conductivity type in the epitaxial layer next to the trench gate and forming a drain contact region and an epitaxial contact region of the first conductivity type with the drain contact region encompassed in the body region and the epitaxial contact region disposed in the epitaxial layer, forming a body contact region of the second conductivity type near a top surface of the body region disposed at a distance from the drain contact region; and

forming a bottom source/emitter/anode electrode layer beneath the semiconductor substrate and forming on a top surface of the epitaxial layer a drain/collector/cathode electrode to contact the trench gate and the drain contact region and further forming a body to source short to electrically short the body contact region to the epitaxial contact region thus forming a TVS structure comprises a TVS diode, a vertical bipolar transistor and a bottom-source metal-oxide-semiconductor field effect transistor (BS-MOSFET) as three parallel connected vertical circuits between the drain/collector/cathode electrode disposed on top of the epitaxial layer and the bottom source/emitter/anode electrode layer.

2. The method of claim 1 wherein:

the forming the drain/collector/cathode electrode to contact the trench gate and the drain region is a step of making the trench gate and the drain/collector/cathode electrode to have a same potential.

3. The method of claim 1 wherein:

the forming the trench gate further comprising a step of forming the trench gate with a predesignated width according to a ratio of an area occupied by the drain contact region to an area occupied by the BS-MOSFET.

4. The method of claim 3 wherein:

the forming the trench gate further comprising a step of forming the trench gate with a predesignated width according to a current flow through the BS-MOSFET required to trigger the vertical bipolar transistor.

5. The method of claim 1 wherein:

the forming the epitaxial layer further comprising forming the epitaxial layer to have a predesignated resistance for adjusting a current flow through the BS-MOSFET to trigger the vertical bipolar transistor.